From c4731fa9ee122fe0ac7ae3f1f05c667cb895e2a5 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Tue, 20 Jun 2023 14:35:48 -0600 Subject: [PATCH] soc/intel/alderlake: Allow channel 0 for DDR5 memory-down MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This matches the change done for DDR4 in commit 8509c25eece8 ("soc/intel/alderlake: Allow channel 0 for memory-down"). Fixes detection of the on-board RAM (Samsung M425R1GB4BB0-CQKOD) on the System76 Lemur Pro 12 (Clevo L140AU). The Clevo L140*U are the only boards in the tree using mixed memory topology. Change-Id: I395f898472a9a8f857fd6b0564b95c787b96080b Signed-off-by: Jeremy Soller Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/75285 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/alderlake/meminit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 2e64e773f8..42b66986e5 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -70,8 +70,8 @@ static const struct soc_mem_cfg soc_mem_cfg[] = { * configuration. */ .half_channel = BIT(0), - /* In mixed topologies, channel 1 is always memory-down. */ - .mixed_topo = BIT(1), + /* In mixed topologies, either channel 0 or 1 can be memory-down. */ + .mixed_topo = BIT(0) | BIT(1), }, }, [MEM_TYPE_LP4X] = {