mb/google/brya/var/crota: enable boot from SSD/ eMMC
- Fix eMMC reset/ enable GPIO pins. - Fix clk_req and clk_src BUG=b:229437061 BRANCH=none TEST=build and boot without error Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: Id16e292ec7557d1780516a267bd752014d98e463 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -84,8 +84,8 @@ chip soc/intel/alderlake
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end
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device ref pcie_rp3 on
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chip soc/intel/common/block/pcie/rtd3
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
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register "srcclk_pin" = "1"
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device generic 0 alias emmc_rtd3 on end
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end
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@ -96,6 +96,7 @@ chip soc/intel/alderlake
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end #PCIE3 BH799BB
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device ref pcie_rp9 off end
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device ref tcss_dma0 on
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chip drivers/intel/usb4/retimer
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register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
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@ -120,10 +121,10 @@ chip soc/intel/alderlake
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end
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end #PCIE8 SD card
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device ref pcie4_0 on
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# Enable CPU PCIE RP 1 using CLK 1
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# Enable CPU PCIE RP 1 using CLK 0
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 1,
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.clk_src = 1,
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.clk_req = 0,
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.clk_src = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end
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