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mb/google/brya/var/crota: enable boot from SSD/ eMMC 

- Fix eMMC reset/ enable GPIO pins.
- Fix clk_req and clk_src

BUG=b:229437061
BRANCH=none
TEST=build and boot without error

Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: Id16e292ec7557d1780516a267bd752014d98e463
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Scott Chao 2022-04-18 11:20:52 +08:00 committed by Felix Held
parent ab58d2b488
commit c480707986
1 changed files with 6 additions and 5 deletions
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11
src/mainboard/google/brya/variants/crota/overridetree.cb
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@ -84,8 +84,8 @@ chip soc/intel/alderlake
end end
device ref pcie_rp3 on device ref pcie_rp3 on
chip soc/intel/common/block/pcie/rtd3 chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
register "srcclk_pin" = "1" register "srcclk_pin" = "1"
device generic 0 alias emmc_rtd3 on end device generic 0 alias emmc_rtd3 on end
end end
@ -96,6 +96,7 @@ chip soc/intel/alderlake
.flags = PCIE_RP_LTR | PCIE_RP_AER, .flags = PCIE_RP_LTR | PCIE_RP_AER,
}" }"
end #PCIE3 BH799BB end #PCIE3 BH799BB
device ref pcie_rp9 off end
device ref tcss_dma0 on device ref tcss_dma0 on
chip drivers/intel/usb4/retimer chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
@ -120,10 +121,10 @@ chip soc/intel/alderlake
end end
end #PCIE8 SD card end #PCIE8 SD card
device ref pcie4_0 on device ref pcie4_0 on
# Enable CPU PCIE RP 1 using CLK 1 # Enable CPU PCIE RP 1 using CLK 0
register "cpu_pcie_rp[CPU_RP(1)]" = "{ register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_req = 1, .clk_req = 0,
.clk_src = 1, .clk_src = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER, .flags = PCIE_RP_LTR | PCIE_RP_AER,
}" }"
end end