vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00

The headers added are generated as per FSP v2162_00.
Previous FSP version was v2117_00.
Changes Include:
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
- Remove DisableDimmMc*Ch* Upds in FspmUpd.h
- Add DisableMc*Ch* Upds in FspmUpd.h
- Few UPDs description update in FspmUpd.h and FspsUpd.h

Change DisableDimmMc*Ch* to DisableMc*Ch* in meminit.c to avoid
compilation failure other change related to UPDs name change will be
part of next patch in relation chain.

BUG=b:187189546
BRANCH=None
TEST=Build and boot ADLRVP using all the patch in relation chain.

Change-Id: Ic8d7980146f1bfc96472ef504cf9f16eee63a13e
Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913
Cq-Depend: chromium:TODO
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54083
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/alderlake/meminit.c

@@ -133,14 +133,14 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da
 		[7] = { &mem_cfg->MemorySpdPtr14, &mem_cfg->MemorySpdPtr15, },
 	};
 	uint8_t *disable_dimm_upds[MRC_CHANNELS] = {
-		&mem_cfg->DisableDimmMc0Ch0,
-		&mem_cfg->DisableDimmMc0Ch1,
-		&mem_cfg->DisableDimmMc0Ch2,
-		&mem_cfg->DisableDimmMc0Ch3,
-		&mem_cfg->DisableDimmMc1Ch0,
-		&mem_cfg->DisableDimmMc1Ch1,
-		&mem_cfg->DisableDimmMc1Ch2,
-		&mem_cfg->DisableDimmMc1Ch3,
+		&mem_cfg->DisableMc0Ch0,
+		&mem_cfg->DisableMc0Ch1,
+		&mem_cfg->DisableMc0Ch2,
+		&mem_cfg->DisableMc0Ch3,
+		&mem_cfg->DisableMc1Ch0,
+		&mem_cfg->DisableMc1Ch1,
+		&mem_cfg->DisableMc1Ch2,
+		&mem_cfg->DisableMc1Ch3,
 	};
 	size_t ch, dimm;