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sb/intel/i82801jx: Add common code for LPC decode 

Change-Id: Id706da33f06ceeec39ea50301130770226f0474e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans 2019-11-09 14:29:04 +01:00 committed by Patrick Georgi
parent fecf77770b
commit c484da1a98
12 changed files with 79 additions and 39 deletions
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15
src/mainboard/asus/p5qc/romstage.c
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@ -51,19 +51,6 @@ static void mb_gpio_init(void)
RCBA32(0x3f00) = 0x00000038;
}
static void ich10_enable_lpc(void)
{
/* Configure serial IRQs.*/
pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN
| COMA_LPC_EN);
/* HW EC */
pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x00000295);
/* ????? */
pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0x001c4701);
}
void mainboard_romstage_entry(void)
{
const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 };
@ -71,7 +58,7 @@ void mainboard_romstage_entry(void)
u8 s3_resume;
/* Set southbridge and Super I/O GPIOs. */
ich10_enable_lpc();
i82801jx_lpc_setup();
mb_gpio_init();
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

3
src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb
View File

@ -45,6 +45,9 @@ chip northbridge/intel/x4x # Northbridge
# Enable PCIe ports 0,2,3 as slots.
register "pcie_slot_implemented" = "0x31"
register "gen1_dec" = "0x00000295"
register "gen2_dec" = "0x001c4701"
device pci 19.0 off end # GBE
device pci 1a.0 on end # USB
device pci 1a.1 on end # USB

3
src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb
View File

@ -45,6 +45,9 @@ chip northbridge/intel/x4x # Northbridge
# Enable PCIe ports 0,2,3 as slots.
register "pcie_slot_implemented" = "0x31"
register "gen1_dec" = "0x00000295"
register "gen2_dec" = "0x001c4701"
device pci 19.0 off end # GBE
device pci 1a.0 on end # USB
device pci 1a.1 on end # USB

3
src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb
View File

@ -45,6 +45,9 @@ chip northbridge/intel/x4x # Northbridge
# Enable PCIe ports 0,2,3 as slots.
register "pcie_slot_implemented" = "0x31"
register "gen1_dec" = "0x00000295"
register "gen2_dec" = "0x001c4701"
device pci 19.0 off end # GBE
device pci 1a.0 on end # USB
device pci 1a.1 on end # USB

2
src/mainboard/asus/p5ql-em/devicetree.cb
View File

@ -49,6 +49,8 @@ chip northbridge/intel/x4x # Northbridge
# Enable PCIe ports 0,1,3,4,5 as slots.
register "pcie_slot_implemented" = "0x3b"
register "gen1_dec" = "0x00000295"
device pci 19.0 off end # GBE
device pci 1a.0 on # USB
subsystemid 0x1043 0x82d4

12
src/mainboard/asus/p5ql-em/romstage.c
View File

@ -117,16 +117,6 @@ static void mb_gpio_init(void)
RCBA8(0x31ff);
}
static void ich10_enable_lpc(void)
{
/* Configure serial IRQs.*/
pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF1_LPC_EN | KBC_LPC_EN
| FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
/* Hardware monitor IO range */
pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x00000295);
}
void mainboard_romstage_entry(void)
{
/* This board has first dimm slot of each channel hooked up to
@ -138,7 +128,7 @@ void mainboard_romstage_entry(void)
u8 s3_resume;
/* Set southbridge and Super I/O GPIOs. */
ich10_enable_lpc();
i82801jx_lpc_setup();
mb_gpio_init();
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

3
src/mainboard/intel/dg43gt/devicetree.cb
View File

@ -42,6 +42,9 @@ chip northbridge/intel/x4x # Northbridge
# Enable PCIe ports 0,2,3 as slots.
register "pcie_slot_implemented" = "0xb"
register "gen1_dec" = "0x00fc0601"
register "gen2_dec" = "0x00fc0291"
device pci 19.0 on end # GBE
device pci 1a.0 on end # USB
device pci 1a.1 on end # USB

15
src/mainboard/intel/dg43gt/romstage.c
View File

@ -53,19 +53,6 @@ static void mb_gpio_init(void)
RCBA32(0x3f00) = 0x0000000b;
}
static void ich10_enable_lpc(void)
{
/* Configure serial IRQs.*/
pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
| MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN
| GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
| COMB_LPC_EN | COMA_LPC_EN);
pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0xfc0601);
pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0xfc0291);
pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0);
}
void mainboard_romstage_entry(void)
{
const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 };
@ -73,7 +60,7 @@ void mainboard_romstage_entry(void)
u8 s3_resume;
/* Set southbridge and Super I/O GPIOs. */
ich10_enable_lpc();
i82801jx_lpc_setup();
mb_gpio_init();
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

1
src/southbridge/intel/i82801jx/Makefile.inc
View File

@ -31,6 +31,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
smm-y += smihandler.c
romstage-y += early_init.c
romstage-y += early_smbus.c
endif

6
src/southbridge/intel/i82801jx/chip.h
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@ -78,6 +78,12 @@ struct southbridge_intel_i82801jx_config {
} pcie_power_limits[6];
uint8_t pcie_hotplug_map[8];
/* Additional LPC IO decode ranges */
uint32_t gen1_dec;
uint32_t gen2_dec;
uint32_t gen3_dec;
uint32_t gen4_dec;
};
#endif /* SOUTHBRIDGE_INTEL_I82801JX_CHIP_H */

54
src/southbridge/intel/i82801jx/early_init.c Normal file
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@ -0,0 +1,54 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/pci_ops.h>
#include "i82801jx.h"
#include "chip.h"
void i82801jx_lpc_setup(void)
{
const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
const struct device *dev = pcidev_on_root(0x1f, 0);
const struct southbridge_intel_i82801jx_config *config;
/* Configure serial IRQs.*/
pci_write_config8(d31f0, D31F0_SERIRQ_CNTL, 0xd0);
/*
* Enable some common LPC IO ranges:
* - 0x2e/0x2f, 0x4e/0x4f often SuperIO
* - 0x60/0x64, 0x62/0x66 often KBC/EC
* - 0x3f0-0x3f5/0x3f7 FDD
* - 0x378-0x37f and 0x778-0x77f LPT
* - 0x2f8-0x2ff COMB
* - 0x3f8-0x3ff COMA
* - 0x208-0x20f GAMEH
* - 0x200-0x207 GAMEL
*/
pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010);
pci_write_config16(d31f0, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
| MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN
| GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
| COMB_LPC_EN | COMA_LPC_EN);
/* Set up generic decode ranges */
if (!dev || !dev->chip_info)
return;
config = dev->chip_info;
pci_write_config32(d31f0, D31F0_GEN1_DEC, config->gen1_dec);
pci_write_config32(d31f0, D31F0_GEN2_DEC, config->gen2_dec);
pci_write_config32(d31f0, D31F0_GEN3_DEC, config->gen3_dec);
pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec);
}

1
src/southbridge/intel/i82801jx/i82801jx.h
View File

@ -234,6 +234,7 @@ int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);
int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
const u8 *buf);
#endif
void i82801jx_lpc_setup(void);
#endif