mb/g/drallion: Enable privacy screen on Drallion variant
Enable ACPI methods to control privacy screen on Drallion devices. Drallion devices may not have a privacy screen and it is up to the EC to determine if the privacy screen is present on the system. BUG=b:142656363 TEST=emerge-drallion coreboot chromeos-bootimage Change-Id: I79d02bb1b25f0deb49ae4bb852b7ed8c21fd31c7 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36045 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -2,6 +2,7 @@
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config BOARD_GOOGLE_BASEBOARD_DRALLION
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def_bool n
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select BOARD_ROMSIZE_KB_32768
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select DRIVERS_GENERIC_GFX
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_HID
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select DRIVERS_INTEL_ISH
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@ -224,7 +224,21 @@ chip soc/intel/cannonlake
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 02.0 on
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chip drivers/generic/gfx
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register "device_count" = "1"
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register "device[0].name" = ""LCD""
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# Address is set following the ACPI spec section A.3.2
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# for an internal panel on the first port of the graphics chip
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register "device[0].addr" = "0x80010400"
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register "device[0].privacy.enabled" = "1"
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register "device[0].privacy.detect_function" = ""\\_SB.PCI0.LPCB.EC0.GPVD""
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register "device[0].privacy.status_function" = ""\\_SB.PCI0.LPCB.EC0.GPVX""
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register "device[0].privacy.enable_function" = ""\\_SB.PCI0.LPCB.EC0.EPVX""
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register "device[0].privacy.disable_function" = ""\\_SB.PCI0.LPCB.EC0.DPVX""
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device generic 0 on end
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end
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end # Integrated Graphics Device
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device pci 04.0 on end # SA Thermal device
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device pci 12.0 on end # Thermal Subsystem
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device pci 12.5 off end # UFS SCS
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@ -31,4 +31,7 @@
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/* Enable DPTF */
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#define EC_ENABLE_DPTF
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/* Enable privacy screen functionality */
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#define EC_ENABLE_PRIVACY
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#endif
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