GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Kill lvds_num_lanes 

Only one value would work with corresponding gma code currently (which one
depends on board). Going forward, it's possible to compute which number can
be used, so there is no need to keep this info around.

Change-Id: Iadc77ef94b02f892860e3ae8d70a0a792758565d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11862
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Vladimir Serbinenko 2015-10-11 02:05:55 +02:00
parent 551cff08d5
commit c48f5ef3cc
16 changed files with 4 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/drivers/intel/gma/i915.h
View File

@ -289,7 +289,6 @@ struct i915_gpu_controller_info
{ {
int use_spread_spectrum_clock; int use_spread_spectrum_clock;
int link_frequency_270_mhz; int link_frequency_270_mhz;
int lvds_num_lanes;
u32 backlight; u32 backlight;
int ndid; int ndid;
u32 did[5]; u32 did[5];

1
src/mainboard/lenovo/t400/devicetree.cb
View File

@ -5,7 +5,6 @@ chip northbridge/intel/gm45
register "gfx.use_spread_spectrum_clock" = "1" register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1" register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "4"
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/socket_BGA956 chip cpu/intel/socket_BGA956

1
src/mainboard/lenovo/t420s/devicetree.cb
View File

@ -14,7 +14,6 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
register "gfx.use_spread_spectrum_clock" = "1" register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1" register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "4"
register "gpu_cpu_backlight" = "0x1155" register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610" register "gpu_pch_backlight" = "0x06100610"

1
src/mainboard/lenovo/t430s/devicetree.cb
View File

@ -14,7 +14,6 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
register "gfx.use_spread_spectrum_clock" = "1" register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1" register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "1"
register "gpu_cpu_backlight" = "0x1155" register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x11551155" register "gpu_pch_backlight" = "0x11551155"

1
src/mainboard/lenovo/t520/devicetree.cb
View File

@ -15,7 +15,6 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
register "gfx.use_spread_spectrum_clock" = "1" register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1" register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "4"
register "gpu_cpu_backlight" = "0x1155" register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610" register "gpu_pch_backlight" = "0x06100610"

1
src/mainboard/lenovo/t530/devicetree.cb
View File

@ -15,7 +15,6 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
register "gfx.use_spread_spectrum_clock" = "1" register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1" register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "1"
register "gpu_cpu_backlight" = "0x1155" register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x11551155" register "gpu_pch_backlight" = "0x11551155"

1
src/mainboard/lenovo/x200/devicetree.cb
View File

@ -5,7 +5,6 @@ chip northbridge/intel/gm45
register "gfx.use_spread_spectrum_clock" = "1" register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1" register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "4"
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/socket_BGA956 chip cpu/intel/socket_BGA956

1
src/mainboard/lenovo/x201/devicetree.cb
View File

@ -39,7 +39,6 @@ chip northbridge/intel/nehalem
register "gpu_pch_backlight" = "0x061a061a" register "gpu_pch_backlight" = "0x061a061a"
register "gfx.use_spread_spectrum_clock" = "1" register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1" register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "4"
chip ec/lenovo/pmh7 chip ec/lenovo/pmh7
device pnp ff.1 on # dummy device pnp ff.1 on # dummy

1
src/mainboard/lenovo/x220/devicetree.cb
View File

@ -15,7 +15,6 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
register "gfx.use_spread_spectrum_clock" = "1" register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1" register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "4"
register "gpu_cpu_backlight" = "0x1155" register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610" register "gpu_pch_backlight" = "0x06100610"

1
src/mainboard/lenovo/x230/devicetree.cb
View File

@ -15,7 +15,6 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
register "gfx.use_spread_spectrum_clock" = "1" register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1" register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "1"
register "gpu_cpu_backlight" = "0x1155" register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x11551155" register "gpu_pch_backlight" = "0x11551155"

1
src/mainboard/packardbell/ms2290/devicetree.cb
View File

@ -39,7 +39,6 @@ chip northbridge/intel/nehalem
register "gpu_pch_backlight" = "0x061a061a" register "gpu_pch_backlight" = "0x061a061a"
register "gfx.use_spread_spectrum_clock" = "0" register "gfx.use_spread_spectrum_clock" = "0"
register "gfx.link_frequency_270_mhz" = "1" register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "4"
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/model_2065x chip cpu/intel/model_2065x

2
src/northbridge/intel/gm45/gma.c
View File

@ -244,7 +244,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency;
data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock)
/ (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4)); / (link_frequency * 8 * 4);
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
hactive, vactive); hactive, vactive);

2
src/northbridge/intel/nehalem/gma.c
View File

@ -792,7 +792,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency;
data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock)
/ (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4)); / (link_frequency * 8 * 4);
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
hactive, vactive); hactive, vactive);

2
src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
View File

@ -313,7 +313,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
link_m1 = ((uint64_t)link_n1 * edid.mode.pixel_clock) / link_frequency; link_m1 = ((uint64_t)link_n1 * edid.mode.pixel_clock) / link_frequency;
data_m1 = ((uint64_t)data_n1 * 18 * edid.mode.pixel_clock) data_m1 = ((uint64_t)data_n1 * 18 * edid.mode.pixel_clock)
/ (link_frequency * 8 * (info->lvds_num_lanes ? : 1)); / (link_frequency * 8);
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
hactive, vactive); hactive, vactive);

2
src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
View File

@ -276,7 +276,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency;
data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock)
/ (link_frequency * 8 * (info->lvds_num_lanes ? : 4)); / (link_frequency * 8 * 4);
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
hactive, vactive); hactive, vactive);

5
util/autoport/sandybridge.go
View File

@ -16,13 +16,9 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
pchLVDS := inteltool.IGD[0xe1180] pchLVDS := inteltool.IGD[0xe1180]
dualChannel := pchLVDS&(3<<2) == (3 << 2) dualChannel := pchLVDS&(3<<2) == (3 << 2)
pipe := (pchLVDS >> 30) & 1 pipe := (pchLVDS >> 30) & 1
data_m1 := inteltool.IGD[0x60030+0x1000*pipe] & 0xffffff
data_n1 := inteltool.IGD[0x60034+0x1000*pipe]
link_m1 := inteltool.IGD[0x60040+0x1000*pipe] link_m1 := inteltool.IGD[0x60040+0x1000*pipe]
link_n1 := inteltool.IGD[0x60044+0x1000*pipe] link_n1 := inteltool.IGD[0x60044+0x1000*pipe]
data_factor := float32(data_m1) / float32(data_n1)
link_factor := float32(link_m1) / float32(link_n1) link_factor := float32(link_m1) / float32(link_n1)
num_lanes := uint32((link_factor/data_factor)*18.0/8.0 + 0.5)
fp0 := inteltool.IGD[0xc6040+8*pipe] fp0 := inteltool.IGD[0xc6040+8*pipe]
dpll := inteltool.IGD[0xc6014+4*pipe] dpll := inteltool.IGD[0xc6014+4*pipe]
pixel_m2 := fp0 & 0xff pixel_m2 := fp0 & 0xff
@ -54,7 +50,6 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
"gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]), "gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]),
"gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001), "gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001),
"gfx.use_spread_spectrum_clock": FormatBool((inteltool.IGD[0xc6200]>>12)&1 != 0), "gfx.use_spread_spectrum_clock": FormatBool((inteltool.IGD[0xc6200]>>12)&1 != 0),
"gfx.lvds_num_lanes": FormatInt32(num_lanes),
"gfx.link_frequency_270_mhz": FormatBool(link_frequency > 200000), "gfx.link_frequency_270_mhz": FormatBool(link_frequency > 200000),
/* FIXME:XX hardcoded. */ /* FIXME:XX hardcoded. */
"gfx.ndid": "3", "gfx.ndid": "3",