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mainboard/google/pyro: Set PL1 override to 12000mW 

Pyro is using APL SoC SKU's with 6W TDP max. As Reef,
the energy calculation is wrong with the current VR solution.
Experiments show that SoC TDP max (6W) can be reached
when RAPL PL1 is set to 12W.
Therefore, we've inserted 12W override after reading the fused value (6W)
so that the system can reach the right performance level.

BUG=chrome-os-partner:58112
BRANCH=master
TEST=emerge-pyro coreboot chromeos-bootimage
Change-Id: I6de22d7b2d107f3d26ecfadd4e0904e68318e656
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17335
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Kevin Chiu 2016-11-09 14:07:30 +08:00 committed by Martin Roth
parent 961d6d45a6
commit c4943d86b0
1 changed files with 5 additions and 0 deletions
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5
src/mainboard/google/reef/variants/pyro/devicetree.cb
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@ -49,6 +49,11 @@ chip soc/intel/apollolake
# Enable DPTF # Enable DPTF
register "dptf_enable" = "1" register "dptf_enable" = "1"
# PL1 override 12000 mW: the energy calculation is wrong with the
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 12W.
register "tdp_pl1_override_mw" = "12000"
# Enable Audio Clock and Power gating # Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1" register "hdaudio_clk_gate_enable" = "1"
register "hdaudio_pwr_gate_enable" = "1" register "hdaudio_pwr_gate_enable" = "1"