sb/intel/i82801gx: Use symbolic name for register, code rework
An original code had a wrong register address 0x27 for AHCI BAR. The value was aligned incidentally by the code specific of the pci_read_config32 function to the correct address 0x24. All 0x24 values in sata.c were changed to the symbolic name PCI_BASE_ADDRESS_5 and the code was optimized. An equivalent code was tested on a real hardware. Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Change-Id: I33509befe86ff6e333c559c87a0f45886d737df9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35737 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -94,7 +94,6 @@ static void sata_init(struct device *dev)
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{
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u32 reg32;
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u16 reg16;
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u32 *ahci_bar;
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u8 ports;
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/* Get the chip configuration */
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@ -117,7 +116,7 @@ static void sata_init(struct device *dev)
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case SATA_MODE_IDE_LEGACY_COMBINED:
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printk(BIOS_DEBUG, "SATA controller in combined mode.\n");
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/* No AHCI: clear AHCI base */
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pci_write_config32(dev, 0x24, 0x00000000);
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pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000);
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/* And without AHCI BAR no memory decoding */
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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reg16 &= ~PCI_COMMAND_MEMORY;
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@ -155,8 +154,11 @@ static void sata_init(struct device *dev)
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/* Interrupt Pin is set by D31IP.PIP */
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pci_write_config8(dev, INTR_LN, 0x0a);
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ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff);
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ahci_bar[3] = config->sata_ports_implemented;
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struct resource *ahci_res = find_resource(dev, PCI_BASE_ADDRESS_5);
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if (ahci_res != NULL)
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/* write AHCI GHC_PI register */
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write32(res2mmio(ahci_res, 0xc, 0),
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config->sata_ports_implemented);
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break;
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default:
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case SATA_MODE_IDE_PLAIN:
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@ -165,7 +167,7 @@ static void sata_init(struct device *dev)
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pci_write_config8(dev, SATA_MAP, 0x00);
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/* No AHCI: clear AHCI base */
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pci_write_config32(dev, 0x24, 0x00000000);
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pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000);
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/* And without AHCI BAR no memory decoding */
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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