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soc/intel/common/block: Add common chip config block 

Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.

For now, adding i2c, gspi and lockdown configuration which will be used
by common code.

BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.

Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2018-05-09 14:55:09 +05:30
parent f513cebd8b
commit c4986eb7f4
52 changed files with 1022 additions and 734 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/google/chell/devicetree.cb
View File

@ -189,7 +189,9 @@ chip soc/intel/skylake
register "SendVrMbxCmd" = "1"
# Lock Down
register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT
}"
device cpu_cluster 0 on
device lapic 0 on end

75
src/mainboard/google/eve/devicetree.cb
View File

@ -169,46 +169,60 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| I2C0 | Touchscreen |
#| I2C1 | Early TPM access |
#| I2C2 | Touchpad |
#| I2C4 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST_PLUS,
.rise_time_ns = 98,
.fall_time_ns = 38,
},
.i2c[1] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 112,
.fall_time_ns = 34,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 186,
.scl_hcnt = 93,
.sda_hold = 36,
}
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 176,
.scl_hcnt = 95,
.sda_hold = 36,
}
},
}"
# Touchscreen
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST_PLUS,
.rise_time_ns = 98,
.fall_time_ns = 38,
}"
# Enable I2C1 bus early for TPM access
register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"
register "i2c[1]" = "{
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 112,
.fall_time_ns = 34,
}"
# Touchpad
register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"
register "i2c[2]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 186,
.scl_hcnt = 93,
.sda_hold = 36,
}
}"
# Audio
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
register "i2c[4]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 176,
.scl_hcnt = 95,
.sda_hold = 36,
}
}"
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
@ -230,9 +244,6 @@ chip soc/intel/skylake
register "tdp_pl2_override" = "15"
register "tcc_offset" = "10"
# Lock Down
register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
device cpu_cluster 0 on
device lapic 0 on end
end

40
src/mainboard/google/fizz/devicetree.cb
View File

@ -275,21 +275,32 @@ chip soc/intel/skylake
register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug
register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio
# Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
# communication before memory is up.
register "gspi[0]" = "{
.speed_mhz = 1,
.early_init = 1,
}"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C5 | Audio |
#+-------------------+---------------------------+
# audio
register "i2c[5]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 194,
.scl_hcnt = 100,
.sda_hold = 36,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 194,
.scl_hcnt = 100,
.sda_hold = 36,
},
},
}"
@ -316,9 +327,6 @@ chip soc/intel/skylake
# Use default SD card detect GPIO configuration
register "sdcard_cd_gpio_default" = "GPP_A7"
# Lock Down
register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
device cpu_cluster 0 on
device lapic 0 on end
end

4
src/mainboard/google/glados/devicetree.cb
View File

@ -187,7 +187,9 @@ chip soc/intel/skylake
register "SendVrMbxCmd" = "1"
# Lock Down
register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end

4
src/mainboard/google/lars/devicetree.cb
View File

@ -184,7 +184,9 @@ chip soc/intel/skylake
register "SendVrMbxCmd" = "2"
# Lock Down
register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end

73
src/mainboard/google/octopus/variants/baseboard/devicetree.cb
View File

@ -54,40 +54,45 @@ chip soc/intel/apollolake
register "hdaudio_pwr_gate_enable" = "1"
register "hdaudio_bios_config_lockdown" = "1"
# digitizer at 400kHz
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 152,
.fall_time_ns = 30,
}"
# Enable I2C5 for audio codec at 400kHz
register "i2c[5]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
}"
# trackpad at 400kHz
register "i2c[6]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 114,
.fall_time_ns = 164,
.data_hold_time_ns = 350,
}"
# touchscreen at 400kHz
register "i2c[7]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 76,
.fall_time_ns = 164,
}"
# Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
# communication before memory is up.
register "gspi[0]" = "{
.speed_mhz = 1,
.early_init = 1,
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | Digitizer |
#| I2C5 | Audio |
#| I2C6 | Trackpad |
#| I2C7 | Touchscreen |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 152,
.fall_time_ns = 30,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
},
.i2c[6] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 114,
.fall_time_ns = 164,
.data_hold_time_ns = 350,
},
.i2c[7] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 76,
.fall_time_ns = 164,
},
}"
register "pnp_settings" = "PNP_PERF_POWER"

73
src/mainboard/google/octopus/variants/bip/devicetree.cb
View File

@ -54,40 +54,45 @@ chip soc/intel/apollolake
register "hdaudio_pwr_gate_enable" = "1"
register "hdaudio_bios_config_lockdown" = "1"
# digitizer at 400kHz
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 152,
.fall_time_ns = 30,
}"
# Enable I2C5 for audio codec at 400kHz
register "i2c[5]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
}"
# trackpad at 400kHz
register "i2c[6]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 114,
.fall_time_ns = 164,
.data_hold_time_ns = 350,
}"
# touchscreen at 400kHz
register "i2c[7]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 76,
.fall_time_ns = 164,
}"
# Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
# communication before memory is up.
register "gspi[0]" = "{
.speed_mhz = 1,
.early_init = 1,
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | Digitizer |
#| I2C5 | Audio |
#| I2C6 | Trackpad |
#| I2C7 | Touchscreen |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 152,
.fall_time_ns = 30,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
},
.i2c[6] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 114,
.fall_time_ns = 164,
.data_hold_time_ns = 350,
},
.i2c[7] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 76,
.fall_time_ns = 164,
},
}"
register "pnp_settings" = "PNP_PERF_POWER"

84
src/mainboard/google/poppy/variants/atlas/devicetree.cb
View File

@ -66,7 +66,6 @@ chip soc/intel/skylake
register "psys_pmax" = "45"
register "tcc_offset" = "10"
register "pch_trip_temp" = "75"
register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
@ -175,51 +174,66 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | Touchscreen |
#| I2C2 | Trackpad |
#| I2C3 | Camera |
#| I2C4 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 98,
.fall_time_ns = 38,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 186,
.scl_hcnt = 93,
.sda_hold = 36,
},
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 98,
.fall_time_ns = 38,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 176,
.scl_hcnt = 95,
.sda_hold = 36,
}
},
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
}"
# Touchscreen
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 98,
.fall_time_ns = 38,
}"
# Trackpad
register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"
register "i2c[2]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 186,
.scl_hcnt = 93,
.sda_hold = 36,
},
}"
# Camera
register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8"
register "i2c[3]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 98,
.fall_time_ns = 38,
}"
# Audio
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
register "i2c[4]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 176,
.scl_hcnt = 95,
.sda_hold = 36,
}
}"
# GSPI0 for cr50 TPM
register "gspi[0]" = "{
.speed_mhz = 1,
.early_init = 1,
}"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,

111
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View File

@ -170,71 +170,85 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
# Touchscreen
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| I2C0 | Touchscreen |
#| I2C1 | H1 |
#| I2C2 | Camera |
#| I2C3 | Pen |
#| I2C4 | Camera |
#| I2C5 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 185,
.scl_hcnt = 90,
.sda_hold = 36,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 185,
.scl_hcnt = 90,
.sda_hold = 36,
},
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 100,
.sda_hold = 36,
},
.early_init = 1,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 97,
.sda_hold = 36,
},
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 97,
.sda_hold = 36,
},
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 98,
.sda_hold = 36,
},
},
}"
# Touchscreen
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
# H1
register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"
register "i2c[1]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 100,
.sda_hold = 36,
},
.early_init = 1,
}"
# Camera
register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"
register "i2c[2]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 97,
.sda_hold = 36,
},
}"
# Pen
register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8"
# Camera
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
register "i2c[4]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 97,
.sda_hold = 36,
},
}"
# Audio
register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8"
register "i2c[5]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 98,
.sda_hold = 36,
},
}"
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
@ -260,9 +274,6 @@ chip soc/intel/skylake
# Use default SD card detect GPIO configuration
register "sdcard_cd_gpio_default" = "GPP_E15"
# Lock Down
register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
# PCH Trip Temperature in degree C
register "pch_trip_temp" = "75"

102
src/mainboard/google/poppy/variants/nami/devicetree.cb
View File

@ -196,58 +196,73 @@ chip soc/intel/skylake
# Touchscreen
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 185,
.scl_hcnt = 90,
.sda_hold = 36,
},
}"
# Trackpad
register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"
register "i2c[1]" = "{
.early_init = 1,
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 185,
.scl_hcnt = 90,
.sda_hold = 36,
},
}"
# Pen
register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"
register "i2c[2]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 185,
.scl_hcnt = 100,
.sda_hold = 36,
},
}"
# Audio
register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8"
register "i2c[3]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 195,
.scl_hcnt = 90,
.sda_hold = 36,
},
}"
# Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
# communication before memory is up.
register "gspi[0]" = "{
.speed_mhz = 1,
.early_init = 1,
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | Touchscreen |
#| I2C1 | Trackpad |
#| I2C2 | Pen |
#| I2C3 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 185,
.scl_hcnt = 90,
.sda_hold = 36,
},
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 185,
.scl_hcnt = 90,
.sda_hold = 36,
},
.early_init = 1,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 185,
.scl_hcnt = 100,
.sda_hold = 36,
},
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 195,
.scl_hcnt = 90,
.sda_hold = 36,
},
},
}"
# Must leave UART0 enabled or SD/eMMC will not work as PCI
@ -270,9 +285,6 @@ chip soc/intel/skylake
register "tcc_offset" = "10" # TCC of 90C
register "psys_pmax" = "101"
# Lock Down
register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
# PCH Trip Temperature in degree C
register "pch_trip_temp" = "75"

132
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View File

@ -179,80 +179,97 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
# Touchscreen
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| I2C0 | Touchscreen |
#| I2C1 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C2 | Trackpad |
#| I2C3 | Pen |
#| I2C4 | Camera |
#| I2C5 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 180,
.scl_hcnt = 90,
.sda_hold = 36,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 180,
.scl_hcnt = 90,
.sda_hold = 36,
},
},
.i2c[1] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 185,
.scl_hcnt = 90,
.sda_hold = 36,
},
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 100,
.sda_hold = 36,
},
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 185,
.scl_hcnt = 90,
.sda_hold = 36,
},
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 100,
.sda_hold = 36,
},
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 100,
.sda_hold = 36,
},
},
}"
# Touch Screen
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
# H1
register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"
# Configure I2C1 for cr50 TPM. Early init is required to set up a BAR
# for TPM communication before memory is up.
register "i2c[1]" = "{
.early_init = 1,
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 185,
.scl_hcnt = 90,
.sda_hold = 36,
},
}"
# Trackpad
register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"
register "i2c[2]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 100,
.sda_hold = 36,
},
}"
# Pen
register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8"
register "i2c[3]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 185,
.scl_hcnt = 90,
.sda_hold = 36,
},
}"
# Camera
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
register "i2c[4]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 100,
.sda_hold = 36,
},
}"
# Audio
register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8"
register "i2c[5]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 100,
.sda_hold = 36,
},
}"
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
@ -278,9 +295,6 @@ chip soc/intel/skylake
# Use default SD card detect GPIO configuration
register "sdcard_cd_gpio_default" = "GPP_E15"
# Lock Down
register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
# PCH Trip Temperature in degree C
register "pch_trip_temp" = "75"

95
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
View File

@ -66,7 +66,6 @@ chip soc/intel/skylake
register "psys_pmax" = "45"
register "tcc_offset" = "10"
register "pch_trip_temp" = "75"
register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
@ -176,59 +175,75 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | Touchscreen |
#| I2C1 | Trackpad |
#| I2C3 | Camera |
#| I2C4 | Audio |
#| I2C5 | Rear Camera & SAR |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 98,
.fall_time_ns = 38,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 186,
.scl_hcnt = 93,
.sda_hold = 36,
},
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 98,
.fall_time_ns = 38,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 176,
.scl_hcnt = 95,
.sda_hold = 36,
}
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 98,
.fall_time_ns = 38,
},
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
}"
# Touchscreen
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 98,
.fall_time_ns = 38,
}"
# Trackpad
register "i2c_voltage[1]" = "I2C_VOLTAGE_1V8"
register "i2c[1]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 186,
.scl_hcnt = 93,
.sda_hold = 36,
},
}"
# Front Camera
register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8"
register "i2c[3]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 98,
.fall_time_ns = 38,
}"
# Audio
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
register "i2c[4]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 176,
.scl_hcnt = 95,
.sda_hold = 36,
}
}"
# Rear Camera & SAR
register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8"
register "i2c[5]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 98,
.fall_time_ns = 38,
}"
# GSPI0 for cr50 TPM
register "gspi[0]" = "{
.speed_mhz = 1,
.early_init = 1,
}"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,

113
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View File

@ -170,68 +170,86 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
# Touchscreen
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| I2C0 | Touchscreen |
#| I2C1 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C2 | Camera |
#| I2C4 | Camera |
#| I2C5 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 180,
.scl_hcnt = 85,
.sda_hold = 36,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 180,
.scl_hcnt = 85,
.sda_hold = 36,
},
},
.i2c[1] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 90,
.sda_hold = 36,
},
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 192,
.scl_hcnt = 90,
.sda_hold = 36,
},
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 90,
.sda_hold = 36,
},
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 90,
.sda_hold = 36,
},
},
}"
# Touchscreen
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
# H1
register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"
# Configure I2C1 for cr50 TPM. Early init is required to set up a BAR
# for TPM communication before memory is up.
register "i2c[1]" = "{
.early_init = 1,
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 90,
.sda_hold = 36,
},
}"
register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"
# Camera
register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"
register "i2c[2]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 192,
.scl_hcnt = 90,
.sda_hold = 36,
},
}"
# Camera
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
register "i2c[4]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 90,
.sda_hold = 36,
},
}"
# Audio
register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8"
register "i2c[5]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 90,
.sda_hold = 36,
},
}"
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
@ -257,9 +275,6 @@ chip soc/intel/skylake
# Use default SD card detect GPIO configuration
register "sdcard_cd_gpio_default" = "GPP_E15"
# Lock Down
register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
# PCH Trip Temperature in degree C
register "pch_trip_temp" = "75"

73
src/mainboard/google/reef/variants/baseboard/devicetree.cb
View File

@ -76,41 +76,44 @@ chip soc/intel/apollolake
register "gpe0_dw2" = "PMC_GPE_N_63_32"
register "gpe0_dw3" = "PMC_GPE_SW_31_0"
# Enable I2C0 for audio codec at 400kHz
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
}"
# Enable I2C2 bus early for TPM at 400kHz
register "i2c[2]" = "{
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 57,
.fall_time_ns = 28,
}"
# touchscreen at 400kHz
register "i2c[3]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 76,
.fall_time_ns = 164,
}"
# trackpad at 400kHz
register "i2c[4]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 114,
.fall_time_ns = 164,
.data_hold_time_ns = 350,
}"
# digitizer at 400kHz
register "i2c[5]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 152,
.fall_time_ns = 30,
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C0 | Audio |
#| I2C2 | TPM |
#| I2C3 | Touchscreen |
#| I2C4 | Trackpad |
#| I2C5 | Digitizer |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
},
.i2c[2] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 57,
.fall_time_ns = 28,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 76,
.fall_time_ns = 164,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 114,
.fall_time_ns = 164,
.data_hold_time_ns = 350,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 152,
.fall_time_ns = 30,
},
}"
# Minimum SLP S3 assertion width 28ms.

73
src/mainboard/google/reef/variants/coral/devicetree.cb
View File

@ -76,41 +76,44 @@ chip soc/intel/apollolake
register "gpe0_dw2" = "PMC_GPE_N_63_32"
register "gpe0_dw3" = "PMC_GPE_SW_31_0"
# Enable I2C0 for audio codec at 400kHz
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
}"
# Enable I2C2 bus early for TPM at 400kHz
register "i2c[2]" = "{
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 57,
.fall_time_ns = 28,
}"
# touchscreen at 400kHz
register "i2c[3]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 76,
.fall_time_ns = 164,
}"
# trackpad at 400kHz
register "i2c[4]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 114,
.fall_time_ns = 164,
.data_hold_time_ns = 350,
}"
# digitizer at 400kHz
register "i2c[5]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 152,
.fall_time_ns = 30,
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C0 | Audio |
#| I2C2 | TPM |
#| I2C3 | Touchscreen |
#| I2C4 | Trackpad |
#| I2C5 | Digitizer |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
},
.i2c[2] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 57,
.fall_time_ns = 28,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 76,
.fall_time_ns = 164,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 114,
.fall_time_ns = 164,
.data_hold_time_ns = 350,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 152,
.fall_time_ns = 30,
},
}"
# Minimum SLP S3 assertion width 28ms.

58
src/mainboard/google/reef/variants/pyro/devicetree.cb
View File

@ -76,33 +76,37 @@ chip soc/intel/apollolake
register "gpe0_dw2" = "PMC_GPE_N_63_32"
register "gpe0_dw3" = "PMC_GPE_SW_31_0"
# Enable I2C0 for audio codec at 400kHz
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
}"
# Enable I2C2 bus early for TPM at 400kHz
register "i2c[2]" = "{
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 50,
.fall_time_ns = 23,
}"
# touchscreen at 400kHz
register "i2c[3]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 76,
.fall_time_ns = 164,
}"
# trackpad at 400kHz
register "i2c[4]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 90,
.fall_time_ns = 164,
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C0 | Audio |
#| I2C2 | TPM |
#| I2C3 | Touchscreen |
#| I2C4 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
},
.i2c[2] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 50,
.fall_time_ns = 23,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 76,
.fall_time_ns = 164,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 90,
.fall_time_ns = 164,
},
}"
# Minimum SLP S3 assertion width 28ms.

71
src/mainboard/google/reef/variants/sand/devicetree.cb
View File

@ -73,40 +73,43 @@ chip soc/intel/apollolake
register "gpe0_dw2" = "PMC_GPE_N_63_32"
register "gpe0_dw3" = "PMC_GPE_SW_31_0"
# Enable I2C0 for audio codec at 400kHz
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
}"
# Enable I2C2 bus early for TPM at 400kHz
register "i2c[2]" = "{
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 57,
.fall_time_ns = 28,
}"
# touchscreen at 400kHz
register "i2c[3]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 76,
.fall_time_ns = 164,
}"
# trackpad at 400kHz
register "i2c[4]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 114,
.fall_time_ns = 164,
}"
# digitizer at 400kHz
register "i2c[5]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 152,
.fall_time_ns = 30,
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C0 | Audio |
#| I2C2 | TPM |
#| I2C3 | Touchscreen |
#| I2C4 | Trackpad |
#| I2C5 | Digitizer |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
},
.i2c[2] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 57,
.fall_time_ns = 28,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 76,
.fall_time_ns = 164,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 114,
.fall_time_ns = 164,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 152,
.fall_time_ns = 30,
},
}"
# Minimum SLP S3 assertion width 28ms.

71
src/mainboard/google/reef/variants/snappy/devicetree.cb
View File

@ -76,40 +76,43 @@ chip soc/intel/apollolake
register "gpe0_dw2" = "PMC_GPE_N_63_32"
register "gpe0_dw3" = "PMC_GPE_SW_31_0"
# Enable I2C0 for audio codec at 400kHz
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 44,
.fall_time_ns = 22,
}"
# Enable I2C2 bus early for TPM at 400kHz
register "i2c[2]" = "{
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 40,
.fall_time_ns = 20,
}"
# touchscreen at 400kHz
register "i2c[3]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 70,
.fall_time_ns = 164,
}"
# trackpad at 400kHz
register "i2c[4]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 20,
.fall_time_ns = 164,
}"
# digitizer at 400kHz
register "i2c[5]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 152,
.fall_time_ns = 30,
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C0 | Audio |
#| I2C2 | TPM |
#| I2C3 | Touchscreen |
#| I2C4 | Trackpad |
#| I2C5 | Digitizer |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 44,
.fall_time_ns = 22,
},
.i2c[2] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 40,
.fall_time_ns = 20,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 70,
.fall_time_ns = 164,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 20,
.fall_time_ns = 164,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 152,
.fall_time_ns = 30,
},
}"
# Minimum SLP S3 assertion width 28ms.

19
src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
View File

@ -25,11 +25,20 @@ chip soc/intel/cannonlake
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "1"
# Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
# communication before memory is up.
register "gspi[0]" = "{
.speed_mhz = 1,
.early_init = 1,
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
}"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"

32
src/mainboard/google/zoombini/variants/meowth/devicetree.cb
View File

@ -34,11 +34,26 @@ chip soc/intel/cannonlake
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "1"
# Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
# communication before memory is up.
register "gspi[0]" = "{
.speed_mhz = 1,
.early_init = 1,
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | Touchscreen Digitizer |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST_PLUS,
.rise_time_ns = 98,
.fall_time_ns = 38,
},
}"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)"
@ -55,13 +70,6 @@ chip soc/intel/cannonlake
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)"
# Touchscreen Digitizer
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST_PLUS,
.rise_time_ns = 98,
.fall_time_ns = 38,
}"
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkSsp0" = "1"
register "PchHdaAudioLinkSsp1" = "1"

19
src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
View File

@ -72,11 +72,20 @@ chip soc/intel/cannonlake
# Enable S0ix
register "s0ix_enable" = "1"
# Audio
register "i2c[3]" = "{
.speed = I2C_SPEED_STANDARD,
.rise_time_ns = 104,
.fall_time_ns = 52,
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| I2C3 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[3] = {
.speed = I2C_SPEED_STANDARD,
.rise_time_ns = 104,
.fall_time_ns = 52,
},
}"
device domain 0 on

17
src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
View File

@ -80,11 +80,18 @@ chip soc/intel/apollolake
register "gpe0_dw2" = "PMC_GPE_N_95_64"
register "gpe0_dw3" = "PMC_GPE_NW_31_0"
# Enable I2C0 for audio codec at 400kHz
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C0 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
},
}"
# Minimum SLP S3 assertion width 28ms.

4
src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
View File

@ -214,7 +214,9 @@ chip soc/intel/skylake
register "VmxEnable" = "0"
# Lock Down
register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end

4
src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
View File

@ -209,7 +209,9 @@ chip soc/intel/skylake
register "sdcard_cd_gpio_default" = "GPP_G5"
# Lock Down
register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end

4
src/mainboard/intel/kunimitsu/devicetree.cb
View File

@ -193,7 +193,9 @@ chip soc/intel/skylake
register "sdcard_cd_gpio_default" = "GPP_A7"
# Lock Down
register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end

4
src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
View File

@ -179,7 +179,9 @@ chip soc/intel/skylake
register "SendVrMbxCmd" = "2"
# Lock Down
register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end

4
src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
View File

@ -186,7 +186,9 @@ chip soc/intel/skylake
register "SendVrMbxCmd" = "2"
# Lock Down
register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end

13
src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
View File

@ -43,9 +43,16 @@ chip soc/intel/apollolake
# [6:0] steps of delay for HS200, each 125ps.
register "emmc_rx_cmd_data_cntl2" = "0x10008"
# Enable I2C0 for proximity sensor at 100kHz
register "i2c[0]" = "{
.speed = I2C_SPEED_STANDARD
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C0 | Proximity Sensor |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_STANDARD
},
}"
device domain 0 on

5
src/soc/intel/apollolake/Kconfig
View File

@ -70,6 +70,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_DSP
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
@ -392,6 +393,10 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
int
default 3
config SOC_INTEL_I2C_DEV_MAX
int
default 8
# Don't include the early page tables in RW_A or RW_B cbfs regions
config RO_REGION_ONLY
string

10
src/soc/intel/apollolake/chip.h
View File

@ -20,6 +20,7 @@
#define _SOC_APOLLOLAKE_CHIP_H_
#include <commonlib/helpers.h>
#include <intelblocks/chip.h>
#include <intelblocks/gspi.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
@ -31,7 +32,6 @@
#define MAX_PCIE_PORTS 6
#define CLKREQ_DISABLED 0xf
#define APOLLOLAKE_I2C_DEV_MAX 8
enum pnp_settings {
PNP_PERF,
@ -40,8 +40,9 @@ enum pnp_settings {
};
struct soc_intel_apollolake_config {
/* GSPI */
struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
/* Common structure containing soc config data required by common code*/
struct soc_intel_common_config common_soc_config;
/*
* Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
@ -98,9 +99,6 @@ struct soc_intel_apollolake_config {
/* Configure serial IRQ (SERIRQ) line. */
enum serirq_mode serirq_mode;
/* I2C bus configuration */
struct dw_i2c_bus_config i2c[APOLLOLAKE_I2C_DEV_MAX];
uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */
uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */
uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */

15
src/soc/intel/apollolake/gspi.c
View File

@ -24,19 +24,10 @@
const struct gspi_cfg *gspi_get_soc_cfg(void)
{
DEVTREE_CONST struct soc_intel_apollolake_config *config;
int devfn = SA_DEVFN_ROOT;
DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);
const struct soc_intel_common_config *common_config;
common_config = chip_get_common_soc_structure();
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
__func__);
return NULL;
}
config = dev->chip_info;
return &config->gspi[0];
return &common_config->gspi[0];
}
uintptr_t gspi_get_soc_early_base(void)

15
src/soc/intel/apollolake/i2c.c
View File

@ -17,24 +17,17 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <drivers/i2c/designware/dw_i2c.h>
#include <intelblocks/chip.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include "chip.h"
const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus)
{
const struct soc_intel_apollolake_config *config;
const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT);
const struct soc_intel_common_config *common_config;
common_config = chip_get_common_soc_structure();
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
__func__);
return NULL;
}
config = dev->chip_info;
return &config->i2c[bus];
return &common_config->i2c[bus];
}
uintptr_t dw_i2c_get_soc_early_base(unsigned int bus)

21
src/soc/intel/apollolake/include/soc/soc_chip.h Normal file
View File

@ -0,0 +1,21 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
#ifndef _SOC_APOLLOLAKE_SOC_CHIP_H_
#define _SOC_APOLLOLAKE_SOC_CHIP_H_
#include "../../chip.h"
#endif /* _SOC_APOLLOLAKE_SOC_CHIP_H_ */

5
src/soc/intel/cannonlake/Kconfig
View File

@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
@ -188,6 +189,10 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
int
default 3
config SOC_INTEL_I2C_DEV_MAX
int
default 6
# Clock divider parameters for 115200 baud rate
config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
hex

1
src/soc/intel/cannonlake/Makefile.inc
View File

@ -41,6 +41,7 @@ ramstage-y += graphics.c
ramstage-y += gspi.c
ramstage-y += gpio.c
ramstage-y += i2c.c
ramstage-y += lockdown.c
ramstage-y += lpc.c
ramstage-y += memmap.c
ramstage-y += nhlt.c

16
src/soc/intel/cannonlake/chip.h
View File

@ -18,6 +18,7 @@
#ifndef _SOC_CHIP_H_
#define _SOC_CHIP_H_
#include <intelblocks/chip.h>
#include <drivers/i2c/designware/dw_i2c.h>
#include <intelblocks/gspi.h>
#include <stdint.h>
@ -30,11 +31,10 @@
#include <soc/usb.h>
#include <soc/vr_config.h>
#define CANNONLAKE_I2C_DEV_MAX 6
struct soc_intel_cannonlake_config {
/* GSPI */
struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
/* Common struct containing soc config data required by common code */
struct soc_intel_common_config common_soc_config;
/* Interrupt Routing configuration.
* If bit7 is 1, the interrupt is disabled. */
@ -201,11 +201,6 @@ struct soc_intel_cannonlake_config {
uint8_t TcoIrqSelect;
uint8_t TcoIrqEnable;
enum {
CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */
CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
} chipset_lockdown;
/*
* Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
@ -281,9 +276,6 @@ struct soc_intel_cannonlake_config {
/* GPIO SD card detect pin */
unsigned int sdcard_cd_gpio;
/* I2C bus configuration */
struct dw_i2c_bus_config i2c[CANNONLAKE_I2C_DEV_MAX];
/* Enable Pch iSCLK */
uint8_t pch_isclk;

16
src/soc/intel/cannonlake/gspi.c
View File

@ -16,6 +16,7 @@
#include <assert.h>
#include <device/device.h>
#include <intelblocks/chip.h>
#include <intelblocks/gspi.h>
#include <intelblocks/spi.h>
#include <soc/iomap.h>
@ -24,19 +25,10 @@
const struct gspi_cfg *gspi_get_soc_cfg(void)
{
DEVTREE_CONST struct soc_intel_cannonlake_config *config;
int devfn = SA_DEVFN_ROOT;
DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);
const struct soc_intel_common_config *common_config;
common_config = chip_get_common_soc_structure();
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
__func__);
return NULL;
}
config = dev->chip_info;
return &config->gspi[0];
return &common_config->gspi[0];
}
uintptr_t gspi_get_soc_early_base(void)

15
src/soc/intel/cannonlake/i2c.c
View File

@ -18,24 +18,17 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <drivers/i2c/designware/dw_i2c.h>
#include <intelblocks/chip.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include "chip.h"
const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus)
{
const struct soc_intel_cannonlake_config *config;
const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT);
const struct soc_intel_common_config *common_config;
common_config = chip_get_common_soc_structure();
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
__func__);
return NULL;
}
config = dev->chip_info;
return &config->i2c[bus];
return &common_config->i2c[bus];
}
uintptr_t dw_i2c_get_soc_early_base(unsigned int bus)

21
src/soc/intel/cannonlake/include/soc/soc_chip.h Normal file
View File

@ -0,0 +1,21 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
#ifndef _SOC_CANNONLAKE_SOC_CHIP_H_
#define _SOC_CANNONLAKE_SOC_CHIP_H_
#include "../../chip.h"
#endif /* _SOC_CANNONLAKE_SOC_CHIP_H_ */

24
src/soc/intel/cannonlake/lockdown.c
View File

@ -16,6 +16,7 @@
#include <arch/io.h>
#include <bootstate.h>
#include <chip.h>
#include <intelblocks/chip.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
@ -27,15 +28,15 @@
#define PCR_DMI_GCS 0x274C
#define PCR_DMI_GCS_BILD (1 << 0)
static void pmc_lockdown_cfg(const struct soc_intel_cannonlake_config *config)
static void pmc_lockdown_cfg(const struct soc_intel_common_config *config)
{
uint8_t *pmcbase;
uint8_t *pmcbase, reg8;
uint32_t reg32, pmsyncreg;
/* PMSYNC */
pmcbase = pmc_mmio_regs();
pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
pmsyncreg |= PMSYNC_LOCK;
pmsyncreg |= PCH2CPU_TPR_CFG_LOCK;
write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
/* Lock down ABASE and sleep stretching policy */
@ -66,7 +67,7 @@ static void dmi_lockdown_cfg(void)
pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
}
static void spi_lockdown_cfg(const struct soc_intel_cannonlake_config *config)
static void fast_spi_lockdown_cfg(const struct soc_intel_common_config *config)
{
/* Set FAST_SPI opcode menu */
fast_spi_set_opcode_menu();
@ -89,24 +90,17 @@ static void spi_lockdown_cfg(const struct soc_intel_cannonlake_config *config)
static void platform_lockdown_config(void *unused)
{
struct soc_intel_cannonlake_config *config;
struct device *dev;
dev = PCH_DEV_SPI;
/* Check if device is valid, else return */
if (dev == NULL || dev->chip_info == NULL)
return;
config = dev->chip_info;
const struct soc_intel_common_config *common_config;
common_config = chip_get_common_soc_structure();
/* SPI lock down configuration */
spi_lockdown_cfg(config);
fast_spi_lockdown_cfg(common_config);
/* DMI lock down configuration */
dmi_lockdown_cfg();
/* PMC lock down configuration */
pmc_lockdown_cfg(config);
pmc_lockdown_cfg(common_config);
}
BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,

4
src/soc/intel/common/block/chip/Kconfig Normal file
View File

@ -0,0 +1,4 @@
config SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
bool
help
Intel Processor common soc/ chip configuration support

10
src/soc/intel/common/block/chip/Makefile.inc Normal file
View File

@ -0,0 +1,10 @@
ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG),y)
bootblock-y += chip.c
romstage-y += chip.c
verstage-y += chip.c
ramstage-y += chip.c
smm-y += chip.c
postcar-y += chip.c
endif

34
src/soc/intel/common/block/chip/chip.c Normal file
View File

@ -0,0 +1,34 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <soc/pci_devs.h>
#include <soc/soc_chip.h>
const struct soc_intel_common_config *chip_get_common_soc_structure(void)
{
const struct soc_intel_common_config *soc_config;
const config_t *config;
int devfn = SA_DEVFN_ROOT;
const struct device *dev = dev_find_slot(0, devfn);
if (!dev || !dev->chip_info)
die("Could not find SA_DEV_ROOT devicetree config!\n");
config = dev->chip_info;
soc_config = &config->common_soc_config;
return soc_config;
}

41
src/soc/intel/common/block/include/intelblocks/chip.h Normal file
View File

@ -0,0 +1,41 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
#ifndef SOC_INTEL_COMMON_BLOCK_CHIP_H
#define SOC_INTEL_COMMON_BLOCK_CHIP_H
#include <intelblocks/gspi.h>
#include <drivers/i2c/designware/dw_i2c.h>
enum {
CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */
CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
};
/*
* This structure will hold data required by common blocks.
* These are soc specific configurations which will be filled by soc.
* We'll fill this structure once during init and use the data in common block.
*/
struct soc_intel_common_config {
int chipset_lockdown;
struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX];
};
/* This function to retrieve soc config structure required by common code */
const struct soc_intel_common_config *chip_get_common_soc_structure(void);
#endif /* SOC_INTEL_COMMON_BLOCK_CHIP_H */

5
src/soc/intel/skylake/Kconfig
View File

@ -56,6 +56,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS
@ -329,6 +330,10 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
int
default 2
config SOC_INTEL_I2C_DEV_MAX
int
default 6
config CPU_BCLK_MHZ
int
default 100

12
src/soc/intel/skylake/chip.c
View File

@ -69,6 +69,14 @@ static void soc_enable(struct device *dev)
dev->ops = &cpu_bus_ops;
}
static int get_lockdown_config(void)
{
const struct soc_intel_common_config *soc_config;
soc_config = chip_get_common_soc_structure();
return soc_config->chipset_lockdown;
}
struct chip_operations soc_intel_skylake_ops = {
CHIP_NAME("Intel Skylake")
.enable_dev = &soc_enable,
@ -145,7 +153,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->SataMode = config->SataMode;
params->LockDownConfigGlobalSmi = config->LockDownConfigGlobalSmi;
params->LockDownConfigRtcLock = config->LockDownConfigRtcLock;
if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
params->LockDownConfigBiosInterface = 0;
params->LockDownConfigBiosLock = 0;
params->LockDownConfigSpiEiss = 0;
@ -173,7 +181,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->SkipMpInit = !config->use_fsp_mp_init;
for (i = 0; i < ARRAY_SIZE(config->i2c); i++)
for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++)
params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
/*

25
src/soc/intel/skylake/chip.h
View File

@ -3,7 +3,7 @@
*
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015 Intel Corporation.
* Copyright (C) 2015-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -22,6 +22,7 @@
#include <arch/acpi_device.h>
#include <device/i2c_simple.h>
#include <drivers/i2c/designware/dw_i2c.h>
#include <intelblocks/chip.h>
#include <intelblocks/gspi.h>
#include <stdint.h>
#include <soc/gpe.h>
@ -33,14 +34,16 @@
#include <soc/usb.h>
#include <soc/vr_config.h>
#define SKYLAKE_I2C_DEV_MAX 6
enum skylake_i2c_voltage {
I2C_VOLTAGE_3V3,
I2C_VOLTAGE_1V8
};
struct soc_intel_skylake_config {
/* Common struct containing soc config data required by common code */
struct soc_intel_common_config common_soc_config;
/*
* Interrupt Routing configuration
* If bit7 is 1, the interrupt is disabled.
@ -273,11 +276,7 @@ struct soc_intel_skylake_config {
/* I2C */
/* Bus voltage level, default is 3.3V */
enum skylake_i2c_voltage i2c_voltage[SKYLAKE_I2C_DEV_MAX];
struct dw_i2c_bus_config i2c[SKYLAKE_I2C_DEV_MAX];
/* GSPI */
struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
enum skylake_i2c_voltage i2c_voltage[CONFIG_SOC_INTEL_I2C_DEV_MAX];
/* Camera */
u8 Cio2Enable;
@ -544,16 +543,6 @@ struct soc_intel_skylake_config {
* 0b - Disabled
*/
u8 eist_enable;
/* Chipset (LPC and SPI) Lock Down
* 1b - coreboot to handle lockdown
* 0b - FSP to handle lockdown
*/
enum {
/* lock according to binary UPD settings */
CHIPSET_LOCKDOWN_FSP,
/* coreboot handles locking */
CHIPSET_LOCKDOWN_COREBOOT,
} chipset_lockdown;
/*
* Activates VR mailbox command for Intersil VR C-state issues.

12
src/soc/intel/skylake/chip_fsp20.c
View File

@ -211,6 +211,14 @@ static void soc_enable(struct device *dev)
dev->ops = &cpu_bus_ops;
}
static int get_lockdown_config(void)
{
const struct soc_intel_common_config *soc_config;
soc_config = chip_get_common_soc_structure();
return soc_config->chipset_lockdown;
}
struct chip_operations soc_intel_skylake_ops = {
CHIP_NAME("Intel 6th Gen")
.enable_dev = &soc_enable,
@ -352,7 +360,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
* do the changes and then lock it back in coreboot during finalize.
*/
tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0;
if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
tconfig->PchLockDownBiosInterface = 0;
params->PchLockDownBiosLock = 0;
params->PchLockDownSpiEiss = 0;
@ -389,7 +397,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->CpuConfig.Bits.SkipMpInit = !config->use_fsp_mp_init;
for (i = 0; i < ARRAY_SIZE(config->i2c); i++)
for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++)
params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)

16
src/soc/intel/skylake/gspi.c
View File

@ -16,6 +16,7 @@
#include <assert.h>
#include <device/device.h>
#include <intelblocks/chip.h>
#include <intelblocks/gspi.h>
#include <intelblocks/spi.h>
#include <soc/iomap.h>
@ -23,19 +24,10 @@
const struct gspi_cfg *gspi_get_soc_cfg(void)
{
DEVTREE_CONST struct soc_intel_skylake_config *config;
int devfn = SA_DEVFN_ROOT;
DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);
const struct soc_intel_common_config *common_config;
common_config = chip_get_common_soc_structure();
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
__func__);
return NULL;
}
config = dev->chip_info;
return &config->gspi[0];
return &common_config->gspi[0];
}
uintptr_t gspi_get_soc_early_base(void)

15
src/soc/intel/skylake/i2c.c
View File

@ -15,6 +15,7 @@
#include <console/console.h>
#include <device/device.h>
#include <intelblocks/chip.h>
#include <drivers/i2c/designware/dw_i2c.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
@ -22,18 +23,10 @@
const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus)
{
const struct soc_intel_skylake_config *config;
const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT);
const struct soc_intel_common_config *common_config;
common_config = chip_get_common_soc_structure();
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
__func__);
return NULL;
}
config = dev->chip_info;
return &config->i2c[bus];
return &common_config->i2c[bus];
}
uintptr_t dw_i2c_get_soc_early_base(unsigned int bus)

21
src/soc/intel/skylake/include/soc/soc_chip.h Normal file
View File

@ -0,0 +1,21 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
#ifndef _SOC_SKYLAKE_SOC_CHIP_H_
#define _SOC_SKYLAKE_SOC_CHIP_H_
#include "../../chip.h"
#endif /* _SOC_SKYLAKE_SOC_CHIP_H_ */

21
src/soc/intel/skylake/lockdown.c
View File

@ -16,6 +16,7 @@
#include <arch/io.h>
#include <bootstate.h>
#include <chip.h>
#include <intelblocks/chip.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
@ -27,7 +28,7 @@
#define PCR_DMI_GCS 0x274C
#define PCR_DMI_GCS_BILD (1 << 0)
static void lpc_lockdown_config(const struct soc_intel_skylake_config *config)
static void lpc_lockdown_config(const struct soc_intel_common_config *config)
{
/* Set Bios Interface Lock, Bios Lock */
if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
@ -63,7 +64,8 @@ static void dmi_lockdown_config(void)
pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
}
static void spi_lockdown_config(const struct soc_intel_skylake_config *config)
static void fast_spi_lockdown_config(const
struct soc_intel_common_config *config)
{
/* Set FAST_SPI opcode menu */
fast_spi_set_opcode_menu();
@ -86,21 +88,14 @@ static void spi_lockdown_config(const struct soc_intel_skylake_config *config)
static void platform_lockdown_config(void *unused)
{
struct soc_intel_skylake_config *config;
struct device *dev;
dev = PCH_DEV_SPI;
/* Check if device is valid, else return */
if (dev == NULL || dev->chip_info == NULL)
return;
config = dev->chip_info;
const struct soc_intel_common_config *common_config;
common_config = chip_get_common_soc_structure();
/* LPC lock down configuration */
lpc_lockdown_config(config);
lpc_lockdown_config(common_config);
/* SPI lock down configuration */
spi_lockdown_config(config);
fast_spi_lockdown_config(common_config);
/* DMI lock down configuration */
dmi_lockdown_config();