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amd/stoneyridge: Add early MTRR setup for new callouts 

Enable the two ranges to be used for the new callouts, AgesaHeapRebase
and AgesaGetHeapBaseInDram.

TEST=Boot grunt w/experimental blob, try different addresses
BUG=b:74518368

Change-Id: Ic7716794dc7d75f849e6e062865d6efbeb4292df
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson 2018-05-07 09:59:10 -06:00 committed by Martin Roth
parent c150a57d29
commit c4be175bdc
2 changed files with 25 additions and 2 deletions
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23
src/soc/amd/stoneyridge/bootblock/bootblock.c
View File

@ -32,7 +32,14 @@
#include <timestamp.h>
#include <halt.h>
/* Set the MMIO Configuration Base Address and Bus Range. */
#if CONFIG_PI_AGESA_TEMP_RAM_BASE < 0x100000
#error "Error: CONFIG_PI_AGESA_TEMP_RAM_BASE must be >= 1MB"
#endif
#if CONFIG_PI_AGESA_CAR_HEAP_BASE < 0x100000
#error "Error: CONFIG_PI_AGESA_CAR_HEAP_BASE must be >= 1MB"
#endif
/* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */
static void amd_initmmio(void)
{
msr_t mmconf;
@ -47,9 +54,23 @@ static void amd_initmmio(void)
/*
* todo: AGESA currently writes variable MTRRs. Once that is
* corrected, un-hardcode this MTRR.
*
* Be careful not to use get_free_var_mtrr/set_var_mtrr pairs
* where all cores execute the path. Both cores within a compute
* unit share MTRRs. Programming core0 has the appearance of
* modifying core1 too. Using the pair again will create
* duplicate copies.
*/
mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_FLASH;
set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_CAR_HEAP;
set_var_mtrr(mtrr, CONFIG_PI_AGESA_CAR_HEAP_BASE,
CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_WRBACK);
mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_TEMPRAM;
set_var_mtrr(mtrr, CONFIG_PI_AGESA_TEMP_RAM_BASE,
CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_UNCACHEABLE);
}
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)

4
src/soc/amd/stoneyridge/include/soc/cpu.h
View File

@ -25,7 +25,9 @@
*
* todo: Revisit this once AGESA no longer programs MTRRs.
*/
#define SOC_EARLY_VMTRR_FLASH 2
#define SOC_EARLY_VMTRR_FLASH 1
#define SOC_EARLY_VMTRR_CAR_HEAP 2
#define SOC_EARLY_VMTRR_TEMPRAM 3
void stoney_init_cpus(struct device *dev);