diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index edf7ed6212..d4e5d2f825 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -469,8 +469,8 @@ chip soc/intel/skylake
 				register "hid" = "ACPI_DT_NAMESPACE_HID"
 				register "uid" = "1"
 				register "compat_string" = ""google,cros-ec-spi""
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)"
-				register "wake" = "GPE0_DW1_06" # GPP_D6
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B0_IRQ)"
+				register "wake" = "GPE0_DW0_01" # GPP_B1
 				device spi 0 on end
 			end # FPMCU
 		end # GSPI #1
diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c
index 2c9b9325d0..a1a0f92eec 100644
--- a/src/mainboard/google/poppy/variants/nami/gpio.c
+++ b/src/mainboard/google/poppy/variants/nami/gpio.c
@@ -409,6 +409,10 @@ static const struct pad_config pantheon_gpio_table[] = {
 };
 
 static const struct pad_config fpmcu_gpio_table[] = {
+	/* B0  : CORE_VID0 ==> FPMCU_INT_L */
+	PAD_CFG_GPI_APIC(GPP_B0, NONE, DEEP),
+	/* B1  : CORE_VID1 ==> FPMCU_INT_L */
+	PAD_CFG_GPI_ACPI_SCI(GPP_B1, 20K_PU, DEEP, INVERT),
 	/* B11 : EXT_PWR_GATE# ==> PCH_FP_PWR_EN */
 	PAD_CFG_GPO(GPP_B11, 1, DEEP),
 	/* B19 : GSPI1_CS# ==> PCH_SPI_FP_CS# */
@@ -421,14 +425,10 @@ static const struct pad_config fpmcu_gpio_table[] = {
 	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
 	/* C3  : SML0CLK ==> TOUCHSCREEN_DIS# */
 	PAD_CFG_GPO(GPP_C3, 0, DEEP),
-	/* C8  : UART0_RXD ==> FPMCU_INT_L */
-	PAD_CFG_GPI_APIC(GPP_C8, NONE, DEEP),
 	/* C9  : UART0_TXD ==> FP_RST_ODL */
 	PAD_CFG_GPO(GPP_C9, 1, DEEP),
 	/* D5  : ISH_I2C0_SDA ==> FPMCU_BOOT0 */
 	PAD_CFG_GPO(GPP_D5, 0, DEEP),
-	/* D6  : ISH_I2C0_SCL ==> FPMCU_INT_L */
-	PAD_CFG_GPI_ACPI_SCI(GPP_D6, 20K_PU, DEEP, INVERT),
 	/* D17 : DMIC_CLK1 ==> NC */
 	PAD_CFG_NC(GPP_D17),
 };