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nb/intel/gm45/bootblock.c: include <arch/pci_io_cfg.h> 

Also rename 'reg' to 'reg32'.

Change-Id: Id741f636162a8a228bca069637993422deb5e09c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes HAOUAS 2021-01-31 08:26:01 +01:00 committed by Patrick Georgi
parent b96c358751
commit c4d1b47ad9
1 changed files with 3 additions and 3 deletions
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6
src/northbridge/intel/gm45/bootblock.c
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@ -1,8 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/bootblock.h>
#include <arch/pci_io_cfg.h>
#include <assert.h>
#include <device/pci_ops.h>
#include <types.h>
#include "gm45.h"
@ -31,7 +31,7 @@ void bootblock_early_northbridge_init(void)
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
*/
const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_HI, 0);
pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg);
pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32);
}