soc/intel/baytrail/southcluster.c: Align with Braswell
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I49e9cef1dfaa62dcfbd1260cec459ff5910ad5da Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43202 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -28,9 +28,8 @@
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#include "chip.h"
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#include "chip.h"
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#include <acpi/acpigen.h>
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#include <acpi/acpigen.h>
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static inline void
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static inline void add_mmio_resource(struct device *dev, int i, unsigned long addr,
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add_mmio_resource(struct device *dev, int i, unsigned long addr,
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unsigned long size)
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unsigned long size)
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{
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{
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mmio_resource(dev, i, addr >> 10, size >> 10);
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mmio_resource(dev, i, addr >> 10, size >> 10);
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}
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}
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@ -58,8 +57,7 @@ static inline int io_range_in_default(int base, int size)
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return 0;
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return 0;
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/* Is it entirely contained? */
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/* Is it entirely contained? */
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if (base >= LPC_DEFAULT_IO_RANGE_LOWER &&
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if (base >= LPC_DEFAULT_IO_RANGE_LOWER && (base + size) < LPC_DEFAULT_IO_RANGE_UPPER)
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(base + size) < LPC_DEFAULT_IO_RANGE_UPPER)
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return 1;
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return 1;
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/* This will return not in range for partial overlaps */
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/* This will return not in range for partial overlaps */
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@ -70,8 +68,7 @@ static inline int io_range_in_default(int base, int size)
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* Note: this function assumes there is no overlap with the default LPC device's
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* Note: this function assumes there is no overlap with the default LPC device's
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* claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
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* claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
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*/
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*/
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static void sc_add_io_resource(struct device *dev, int base, int size,
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static void sc_add_io_resource(struct device *dev, int base, int size, int index)
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int index)
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{
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{
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struct resource *res;
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struct resource *res;
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@ -113,11 +110,6 @@ static void sc_read_resources(struct device *dev)
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sc_add_io_resources(dev);
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sc_add_io_resources(dev);
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}
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}
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static void sc_rtc_init(void)
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{
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cmos_init(rtc_failure());
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}
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/*
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/*
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* The UART hardware loses power while in suspend. Because of this the kernel
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* The UART hardware loses power while in suspend. Because of this the kernel
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* can hang because it doesn't re-initialize serial ports it is using for
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* can hang because it doesn't re-initialize serial ports it is using for
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@ -176,15 +168,14 @@ static void sc_init(struct device *dev)
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/* Route SCI to IRQ9 */
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/* Route SCI to IRQ9 */
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write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9);
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write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9);
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sc_rtc_init();
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cmos_init(rtc_failure());
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if (config->disable_slp_x_stretch_sus_fail) {
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if (config->disable_slp_x_stretch_sus_fail) {
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printk(BIOS_DEBUG, "Disabling slp_x stretching.\n");
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printk(BIOS_DEBUG, "Disabling slp_x stretching.\n");
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write32(gen_pmcon1,
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write32(gen_pmcon1, read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP);
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read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP);
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} else {
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} else {
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write32(gen_pmcon1,
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write32(gen_pmcon1, read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP);
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read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP);
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}
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}
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if (acpi_is_wakeup_s3())
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if (acpi_is_wakeup_s3())
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@ -200,7 +191,7 @@ static void sc_disable_devfn(struct device *dev)
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{
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{
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void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS);
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void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS);
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void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2);
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void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2);
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uint32_t mask = 0;
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uint32_t mask = 0;
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uint32_t mask2 = 0;
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uint32_t mask2 = 0;
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switch (dev->path.pci.devfn) {
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switch (dev->path.pci.devfn) {
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@ -475,8 +466,7 @@ void southcluster_enable_dev(struct device *dev)
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/* Ensure memory, io, and bus master are all disabled */
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/* Ensure memory, io, and bus master are all disabled */
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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reg16 &= ~(PCI_COMMAND_MASTER |
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reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
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PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
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pci_write_config16(dev, PCI_COMMAND, reg16);
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pci_write_config16(dev, PCI_COMMAND, reg16);
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/* Place device in D3Hot */
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/* Place device in D3Hot */
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@ -522,7 +512,7 @@ static struct device_operations device_ops = {
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.read_resources = sc_read_resources,
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.read_resources = sc_read_resources,
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.set_resources = pci_dev_set_resources,
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.set_resources = pci_dev_set_resources,
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.acpi_inject_dsdt = southcluster_inject_dsdt,
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.acpi_inject_dsdt = southcluster_inject_dsdt,
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.write_acpi_tables = acpi_write_hpet,
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.write_acpi_tables = acpi_write_hpet,
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.init = sc_init,
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.init = sc_init,
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.enable = southcluster_enable_dev,
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.enable = southcluster_enable_dev,
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.scan_bus = scan_static_bus,
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.scan_bus = scan_static_bus,
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@ -546,7 +536,7 @@ static void finalize_chipset(void *unused)
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void *gcs = (void *)(RCBA_BASE_ADDRESS + GCS);
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void *gcs = (void *)(RCBA_BASE_ADDRESS + GCS);
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void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2);
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void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2);
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void *etr = (void *)(PMC_BASE_ADDRESS + ETR);
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void *etr = (void *)(PMC_BASE_ADDRESS + ETR);
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u8 *spi = (u8 *)SPI_BASE_ADDRESS;
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uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS;
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struct spi_config cfg;
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struct spi_config cfg;
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/* Set the lock enable on the BIOS control register */
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/* Set the lock enable on the BIOS control register */
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