util/spd_tools: Add support for LP5X SPDs

This commit adds support for LP5X SPDs. The SPD format is identical to
LP5 except that the memory type is set to 0x15 instead of 0x13. Since
they are essentially the same, LP5/5X parts share the same parts JSON
file and SPD directory. LP5X parts are distinguished by the optional
`lp5x` attribute. This commit also updates two existing LP5X memory
parts with the correct attribute.

BUG=b:242765117
TEST=Generated SPDs, verified that SPDs generated from LP5X parts match
their LP5 counterparts except for memory type byte.

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I67df22bc3fd8ea45fe4dad16b8579351eb4d0d8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>

spd/lp5/memory_parts.json

@@ -107,7 +107,8 @@
                 "diesPerPackage": 2,
                 "bitWidthPerChannel": 16,
                 "ranksPerChannel": 1,
-                "speedMbps": 7500
+                "speedMbps": 7500,
+                "lp5x": true
             }
         },
         {
@@ -117,7 +118,8 @@
                 "diesPerPackage": 4,
                 "bitWidthPerChannel": 16,
                 "ranksPerChannel": 2,
-                "speedMbps": 7500
+                "speedMbps": 7500,
+                "lp5x": true
             }
         }
     ]

spd/lp5/platforms_manifest.generated.txt

@@ -3,4 +3,4 @@
 
 MTL,set-0
 ADL,set-0
-SBR,set-1
+MDN,set-1

spd/lp5/set-1/spd-7.hex

@@ -1,4 +1,4 @@
-23 11 13 0E 86 21 95 18 00 40 00 00 02 02 00 00
+23 11 15 0E 86 21 95 18 00 40 00 00 02 02 00 00
 00 00 03 00 00 00 00 00 2B 00 90 A8 90 C0 08 60
 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

spd/lp5/set-1/spd-8.hex

@@ -1,4 +1,4 @@
-23 11 13 0E 86 21 B5 18 00 40 00 00 0A 02 00 00
+23 11 15 0E 86 21 B5 18 00 40 00 00 0A 02 00 00
 00 00 03 00 00 00 00 00 2B 00 90 A8 90 C0 08 60
 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

util/spd_tools/README.md

@@ -8,9 +8,9 @@ The memory technologies currently supported are:
 *   LPDDR4x - based on the JESD209-4C spec and Intel recommendations
     (docs #616599, #610202, #634730).
 *   DDR4 - based on the JESD79-4C and Jedec 4.1.2.L-5 R29 v103 specs.
-*   LPDDR5 - based on the LPDDR5 spec JESD209-5B, the SPD spec SPD4.1.2.M-2 (the
+*   LPDDR5/5X - based on the LPDDR5 spec JESD209-5B, the SPD spec SPD4.1.2.M-2
-    LPDDR3/4 spec is used since JEDEC has not released an SPD spec for LPDDR5),
+    (the LPDDR3/4 spec is used since JEDEC has not released an SPD spec for
-    and Intel recommendations in advisory #616599.
+    LPDDR5), and Intel recommendations in advisory #616599.
 
 There are two tools provided to assist with generating SPDs and Makefiles to
 integrate into the coreboot build. These tools can also be used to allocate DRAM
@@ -317,6 +317,9 @@ string like "9 10 11 12 14".
 
 #### Optional
 
+*   `lp5x`: If this is an LP5X part. SPD format is identical for LP5/5X aside
+    from the memory type byte.
+
 *   `trfcabNs`: Minimum Refresh Recovery Delay Time (tRFCab) for all banks in
     nanoseconds. As per JESD209-5B, this is dependent on the density per die.
     Default values used:

util/spd_tools/src/spd_gen/lp5.go

@@ -25,6 +25,8 @@ type LP5MemAttributes struct {
 	 * All the following parameters are optional and required only if the part requires
 	 * special parameters as per the datasheet.
 	 */
+	LP5X bool
+
 	/* Timing parameters */
 	TRFCABNs   int
 	TRFCPBNs   int
@@ -70,6 +72,7 @@ type LP5Set struct {
 	otherOptionalFeatures  byte
 	busWidthEncoding  byte
 	speedToTCKMinPs map[int]int
+	lp5xOverrideType byte
 }
 
 /* ------------------------------------------------------------------------------------------ */
@@ -128,8 +131,10 @@ const (
 
 	/*
 	 * As per advisory #616599, ADL MRC expects LPDDR5 memory type = 0x13.
+	 * From JEDEC spec, LPDDR5X memory type = 0x15.
 	 */
 	LP5SPDValueMemoryType  = 0x13
+	LP5XSPDValueMemoryType = 0x15
 
 	/*
 	 * From JEDEC spec:
@@ -209,6 +214,12 @@ var LP5SetInfo = map[int]LP5Set{
 			 6400 : 1250, /* 1 / (6400 / 2 / 4) */
 			 5500 : 1455, /* 1 / (5500 / 2 / 4) */
 		},
+
+		/*
+		 * Intel FSP code doesn't distinguish between LP5/5X, existing
+		 * SPDs have been using 0x13 for both types.
+		 */
+		lp5xOverrideType: LP5SPDValueMemoryType,
 	},
 	1: {
 		SPDRevision: LP5SPDValueRevision1_1,
@@ -234,6 +245,8 @@ var LP5SetInfo = map[int]LP5Set{
 		 * Set to 0x02.
 		 */
 		busWidthEncoding: 0x02,
+
+		lp5xOverrideType: LP5XSPDValueMemoryType,
 	},
 }
 
@@ -386,7 +399,7 @@ var LP5SpeedMbpsToSPDEncoding = map[int]LP5SpeedParams{
 var LP5SPDAttribTable = map[int]LP5SPDAttribTableEntry{
 	LP5SPDIndexSize:                  {constVal: LP5SPDValueSize},
 	LP5SPDIndexRevision:              {getVal: LP5EncodeSPDRevision},
-	LP5SPDIndexMemoryType:            {constVal: LP5SPDValueMemoryType},
+	LP5SPDIndexMemoryType:            {getVal: LP5EncodeMemoryType},
 	LP5SPDIndexModuleType:            {constVal: LP5SPDValueModuleType},
 	LP5SPDIndexDensityBanks:          {getVal: LP5EncodeDensityBanks},
 	LP5SPDIndexAddressing:            {getVal: LP5EncodeSdramAddressing},
@@ -459,6 +472,17 @@ func LP5GetBankGroups(memAttribs *LP5MemAttributes) int {
 	return LP5BankArchToSPDEncoding[LP5GetBankArch(memAttribs)].BankGroups
 }
 
+func LP5EncodeMemoryType(memAttribs *LP5MemAttributes) byte {
+	var b byte = LP5SPDValueMemoryType
+
+	if memAttribs.LP5X {
+		if f, ok := LP5SetInfo[LP5CurrSet]; ok {
+			b = f.lp5xOverrideType
+		}
+	}
+	return b
+}
+
 func LP5EncodeDensityBanks(memAttribs *LP5MemAttributes) byte {
 	var b byte