Change #ifdef and #if defined CONFIG_ bools to #if IS_ENABLED()
Kconfigs symbols of type bool are always defined, and can be tested with the IS_ENABLED() macro. symbol type except string. Change-Id: Ic4ba79f519ee2a53d39c10859bbfa9c32015b19d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10885 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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c4e49f6262
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@ -55,7 +55,7 @@ void main(void)
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//bootblock_mainboard_init();
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}
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#ifdef CONFIG_BOOTBLOCK_CONSOLE
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#if IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)
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console_init();
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exception_init();
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#endif
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@ -56,7 +56,7 @@ void main(void)
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//bootblock_mainboard_init();
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}
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#ifdef CONFIG_BOOTBLOCK_CONSOLE
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#if IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)
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console_init();
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exception_init();
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#endif
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@ -19,7 +19,7 @@ void set_var_mtrr(
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wrmsr(MTRRphysMask_MSR(reg), maskm);
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}
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#if !defined(CONFIG_CACHE_AS_RAM) || !CONFIG_CACHE_AS_RAM
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#if !IS_ENABLED(CONFIG_CACHE_AS_RAM)
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static void cache_ramstage(void)
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{
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/* Enable caching for lower 1MB and ram stage using variable mtrr */
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@ -55,7 +55,7 @@
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* disabled.
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* @{
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*/
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#if defined(CONFIG_DEBUG_RAM_SETUP) && (CONFIG_DEBUG_RAM_SETUP)
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#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
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#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__)
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#else
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#define printram(x, ...)
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@ -55,7 +55,7 @@
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/**
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* \brief printk macro for SMBus debugging
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*/
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#if defined(CONFIG_DEBUG_SMBUS) && (CONFIG_DEBUG_SMBUS)
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#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
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#define printsmbus(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__)
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#else
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#define printsmbus(x, ...)
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@ -34,7 +34,7 @@
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_etext = .;
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} : to_load
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#ifdef CONFIG_COVERAGE
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#if IS_ENABLED(CONFIG_COVERAGE)
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.ctors : {
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. = ALIGN(0x100);
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__CTOR_LIST__ = .;
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@ -30,7 +30,7 @@ SECTIONS
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/* C read-only data. */
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. = ALIGN(16);
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#ifdef CONFIG_COVERAGE
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#if IS_ENABLED(CONFIG_COVERAGE)
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__CTOR_LIST__ = .;
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*(.ctors);
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LONG(0);
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@ -460,7 +460,7 @@ static void gma_func0_init(struct device *dev)
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dp.panel_power_up_delay = conf->gpu_panel_power_up_delay;
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dp.panel_power_cycle_delay = conf->gpu_panel_power_cycle_delay;
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#ifdef CONFIG_CHROMEOS
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#if IS_ENABLED(CONFIG_CHROMEOS)
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init_fb = developer_mode_enabled() || recovery_mode_enabled();
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#endif
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lightup_ok = panel_lightup(&dp, init_fb);
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@ -45,7 +45,7 @@ extern unsigned int ddr3_init_tab_1066[];
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#define CONFIG_DRAM_FREQ 667
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extern unsigned int ddr3_init_tab_1333[];
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#endif
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#ifdef CONFIG_CYGNUS_DDR800
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#if IS_ENABLED(CONFIG_CYGNUS_DDR800)
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#define CONFIG_DRAM_FREQ 800
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extern unsigned int ddr3_init_tab_1600[];
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#endif
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@ -64,7 +64,7 @@ int cygnus_phy_powerup(void);
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void ddr_init2(void);
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void PRE_SRX(void);
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#if defined(CONFIG_SOC_BROADCOM_CYGNUS)
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#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
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void PRE_SRX(void)
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{
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uint32_t readvalue = 0;
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@ -281,7 +281,7 @@ void iproc_clear_ecc_syndrome(void)
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}
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#endif
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#if defined(CONFIG_SOC_BROADCOM_CYGNUS)
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#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
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uint32_t iproc_get_ddr3_clock_mhz(uint32_t unit)
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{
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uint32_t ndiv, mdiv, pdiv, ddrclk, data;
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@ -306,7 +306,7 @@ uint32_t iproc_get_ddr3_clock_mhz(uint32_t unit)
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#endif
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#if defined(CONFIG_SOC_BROADCOM_CYGNUS)
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#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
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int cygnus_phy_powerup(void)
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{
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@ -1187,7 +1187,7 @@ static int clear_ddr(uint32_t offset, uint32_t size)
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extern void restore_shmoo_config(and28_shmoo_config_param_t *shmoo_control_para);
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#endif
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#if defined(CONFIG_SOC_BROADCOM_CYGNUS)
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#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
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static int simple_ddr_crc32_check(void)
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{
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return 0;
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@ -1226,7 +1226,7 @@ void ddr_init2(void)
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uint32_t status, sku_id, ddr_clk, dev_id = 0;
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uint32_t unit = 0;
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uint32_t skip_shmoo = 0;
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#if defined(CONFIG_SOC_BROADCOM_CYGNUS)
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#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
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uint32_t pwrctli0 = reg32_read((volatile uint32_t *)IHOST_SCU_POWER_STATUS) & 0x3;
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skip_shmoo = reg32_read((volatile uint32_t *)CRMU_IHOST_POR_WAKEUP_FLAG) & 0x1;
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@ -1239,22 +1239,22 @@ void ddr_init2(void)
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skip_shmoo = 1;
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reg32_write((volatile uint32_t *)IHOST_GTIM_GLOB_CTRL, reg32_read((volatile uint32_t *)IHOST_GTIM_GLOB_CTRL)| 0x1);
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}
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#endif /* defined(CONFIG_SOC_BROADCOM_CYGNUS) */
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#endif /* IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) */
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dev_id = dev_id;
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#ifdef CONFIG_SOC_BROADCOM_CYGNUS
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#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
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and28_shmoo_dram_info_t sdi;
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and28_shmoo_config_param_t config_param;
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#endif
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#ifndef CONFIG_SOC_BROADCOM_CYGNUS
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#if !IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
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dev_id = (reg32_read((volatile uint32_t *)ChipcommonA_ChipID)) & 0x0000ffff;
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#else
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dev_id = 0x5800;
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cygnus_phy_powerup();
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#endif
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#if defined(CONFIG_SOC_BROADCOM_CYGNUS)
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#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
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sku_id = (reg32_read((volatile uint32_t *)ROM_S0_IDM_IO_STATUS) >> 8) & 0x0f;
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#else
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sku_id = (reg32_read((volatile uint32_t *)ROM_S0_IDM_IO_STATUS) >> 2) & 0x03;
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@ -1279,7 +1279,7 @@ void ddr_init2(void)
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goto done;
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}
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printk(BIOS_INFO, "DDR type: DDR%d\n", (ddr_type == 1)? 3 : 4);
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#elif defined(CONFIG_SOC_BROADCOM_CYGNUS)
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#elif IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
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ddr_type = 1;
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#else
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ddr_type = reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS) & 0x1;
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}
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#endif /* defined(CONFIG_IPROC_P7) */
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#if defined(CONFIG_SOC_BROADCOM_CYGNUS) || defined(CONFIG_IPROC_P7)
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#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) || defined(CONFIG_IPROC_P7)
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/* Get the DDR S1 and S2 out of reset */
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reg32_write((volatile uint32_t *)DDR_S1_IDM_RESET_CONTROL, 0);
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reg32_write((volatile uint32_t *)DDR_S2_IDM_RESET_CONTROL, 0);
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reg32_write((volatile uint32_t *)DDR_S2_IDM_RESET_CONTROL, 0);
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/* Set the ddr_ck to 400 MHz, 2x memc clock */
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reg32_write_masked((volatile uint32_t *)DDR_S1_IDM_IO_CONTROL_DIRECT, 0xfff << 16, /*ddr_clk*/ 0x190 << 16);
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#endif /* defined(CONFIG_SOC_BROADCOM_CYGNUS) || defined(CONFIG_IPROC_P7) */
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#endif /* IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) || defined(CONFIG_IPROC_P7) */
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#if defined(CONFIG_IPROC_P7)
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if (is_ddr_32bit()) {
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return;
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}
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#if defined(CONFIG_SOC_BROADCOM_CYGNUS)
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#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
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if(!skip_shmoo)
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{
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printk(BIOS_INFO, "ddr_init2: Calling soc_and28_shmoo_dram_info_set\n");
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#error "DRAM config is not set"
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#endif
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#if defined(CONFIG_SOC_BROADCOM_CYGNUS)
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#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
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if(!skip_shmoo)
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{
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printk(BIOS_INFO, "ddr_init2: Calling soc_and28_shmoo_phy_init\n");
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ddr_init_regs(ddr3_init_tab_1333);
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break;
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#endif
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#if (defined(CONFIG_DDR750) || defined(CONFIG_CYGNUS_DDR800))
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#if (defined(CONFIG_DDR750) || IS_ENABLED(CONFIG_CYGNUS_DDR800))
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case 750:
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case 800:
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ddr_init_regs(ddr3_init_tab_1600);
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/* Start the DDR */
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reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_00, 0x01);
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#if defined(CONFIG_SOC_BROADCOM_CYGNUS)
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#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
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if(!skip_shmoo)
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{
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while(!(reg32_read((volatile uint32_t *)DDR_DENALI_CTL_175) & 0x100));
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//dump_phy_regs();
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#if defined(CONFIG_SOC_BROADCOM_CYGNUS)
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#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
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/* SRX */
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if(skip_shmoo)
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{
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"ldr r5, [r3]\n"
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"mov lr, #0\n"
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"mov pc, r5\n");
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#endif /* defined(CONFIG_SOC_BROADCOM_CYGNUS) */
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#endif /* IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) */
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done:
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/* Reclaim everything we have previously allocated for temporary usage. */
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@ -1488,7 +1488,7 @@ const unsigned int ddr3_init_tab_1333[] = {
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};
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#endif
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#ifdef CONFIG_CYGNUS_DDR800
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#if IS_ENABLED(CONFIG_CYGNUS_DDR800)
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const unsigned int ddr3_init_tab_1600[] = {
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14, 0x01000000,
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36, 0x0a140a0a,
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@ -35,7 +35,7 @@
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#define DEFAULT_RCBA 0xfed1c000
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#endif
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#ifdef CONFIG_BOARD_EMULATION_QEMU_X86_Q35
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#if IS_ENABLED(CONFIG_BOARD_EMULATION_QEMU_X86_Q35)
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/*
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* Qemu has the fw_cfg interface at 0x510. Move the pmbase to a
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* non-conflicting address. No need to worry about speedstep, it
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