mb/google/brya: Finish support for ChromeOS GPIOs
BUG=b:181887865 TEST=`crossystem` shows correct state of WP signal when toggled Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: If49ca1d70cc36ab74d70e858336679c0a9a3258e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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@ -12,14 +12,14 @@ void fill_lb_gpios(struct lb_gpios *gpios)
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{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
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{-1, ACTIVE_HIGH, 0, "power"},
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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int get_write_protect_state(void)
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{
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/* No write protect */
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return 0;
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return gpio_get(GPIO_PCH_WP);
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}
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void mainboard_chromeos_acpi_generate(void)
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@ -10,5 +10,9 @@
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#define EC_SCI_GPI GPE0_ESPI
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/* EC wake is EC_PCH_INT which is routed to GPP_F17 pin */
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#define GPE_EC_WAKE GPE0_DW2_17
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/* WP signal to PCH */
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#define GPIO_PCH_WP GPP_E15
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/* EC in RW or RO */
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#define GPIO_EC_IN_RW GPP_F18
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#endif /* __BASEBOARD_GPIO_H__ */
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