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drivers/intel/fsp2_0: Send post codes around calls to the blobs 

By design, FSP will send POST codes to port 80. In this case we have
both coreboot and FSP pushing post codes, which may make debugging
harder. In order to get a clear picture of where FSP execution begins
and ends, send post codes before and after any call to the FSP blobs.

Note that sending a post code both before and after is mostly useful
on chromeec enabled boards, where the EC console will provide a
historic list of post codes.

Change-Id: Icfd22b4f6d9e91b01138f97efd711d9204028eb1
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14951
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Alexandru Gagniuc 2016-05-23 12:16:58 -07:00 committed by Martin Roth
parent c16918ac11
commit c4ea8f7d3f
3 changed files with 14 additions and 5 deletions
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3
src/drivers/intel/fsp2_0/memory_init.c
View File

@ -51,9 +51,10 @@ static enum fsp_status do_fsp_memory_init(void **hob_list_ptr,
printk(BIOS_SPEW, "\t%p: raminit_upd\n", &fspm_upd);
printk(BIOS_SPEW, "\t%p: hob_list ptr\n", hob_list_ptr);
post_code(POST_FSP_MEMORY_INIT);
timestamp_add_now(TS_FSP_MEMORY_INIT_START);
status = fsp_raminit(&fspm_upd, hob_list_ptr);
post_code(0x37);
post_code(POST_FSP_MEMORY_INIT);
timestamp_add_now(TS_FSP_MEMORY_INIT_END);
printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status);

14
src/drivers/intel/fsp2_0/notify.c
View File

@ -38,17 +38,23 @@ enum fsp_status fsp_notify(enum fsp_notify_phase phase)
printk(BIOS_DEBUG, "FspNotify %x\n", (uint32_t) phase);
if (phase == AFTER_PCI_ENUM)
if (phase == AFTER_PCI_ENUM) {
timestamp_add_now(TS_FSP_BEFORE_ENUMERATE);
else if (phase == READY_TO_BOOT)
post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE);
} else if (phase == READY_TO_BOOT) {
timestamp_add_now(TS_FSP_BEFORE_FINALIZE);
post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE);
}
ret = fspnotify(&notify_params);
if (phase == AFTER_PCI_ENUM)
if (phase == AFTER_PCI_ENUM) {
timestamp_add_now(TS_FSP_AFTER_ENUMERATE);
else if (phase == READY_TO_BOOT)
post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE);
} else if (phase == READY_TO_BOOT) {
timestamp_add_now(TS_FSP_AFTER_FINALIZE);
post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE);
}
return ret;
}

2
src/drivers/intel/fsp2_0/silicon_init.c
View File

@ -42,10 +42,12 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr)
platform_fsp_silicon_init_params_cb(&upd);
timestamp_add_now(TS_FSP_SILICON_INIT_START);
post_code(POST_FSP_SILICON_INIT);
silicon_init = (void *) (hdr->image_base +
hdr->silicon_init_entry_offset);
status = silicon_init(&upd);
timestamp_add_now(TS_FSP_SILICON_INIT_END);
post_code(POST_FSP_SILICON_INIT);
printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
return status;