mb/asrock/h110m: use SSDT generator for SuperIO
Modifies the device tree to use the ACPI SSDT generator[1] for NCT6791D SuperIO, dropping the need to include code from the superio.asl, which was inherited from another chip (NCT6776) and required fixes. SSDT gen support for Nuvoton NCT6791D chip was added in the previous patch [2]. [1] https://review.coreboot.org/c/coreboot/+/33033 [2] https://review.coreboot.org/c/coreboot/+/36379 Change-Id: I57b67d10968e5e035536bcb0d8329ce09d50194b Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Maxim Polyakov
Felix Held
parent
facbf47224
commit
c4f77d943a
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@ -1,26 +1 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define SUPERIO_DEV SIO0
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#define SUPERIO_PNP_BASE 0x2e
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#define NCT6776_SHOW_PP
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#define NCT6776_SHOW_SP1
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#define NCT6776_SHOW_KBC
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#define NCT6776_SHOW_HWM
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#undef NCT6776_SHOW_GPIO
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#include <superio/nuvoton/nct6776/acpi/superio.asl>
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@ -326,101 +326,108 @@ chip soc/intel/skylake
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device pci 1e.6 off end # SDCard
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device pci 1e.6 off end # SDCard
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device pci 1f.0 on # LPC bridge
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device pci 1f.0 on # LPC bridge
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subsystemid 0x1849 0x1a43
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subsystemid 0x1849 0x1a43
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chip superio/nuvoton/nct6791d
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device pnp 2e.0 off end # Floppy
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device pnp 2e.1 on
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# Global Control Registers
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# Device IRQ Polarity
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irq 0x13 = 0x00
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irq 0x14 = 0x00
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# Global Option
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irq 0x24 = 0xfb
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irq 0x27 = 0x10
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# Multi Function
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irq 0x1a = 0xb0
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irq 0x1b = 0xe6
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irq 0x2a = 0x04
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irq 0x2c = 0x40
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irq 0x2d = 0x03
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# Parallel Port
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chip superio/common
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io 0x60 = 0x0378
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device pnp 2e.0 on # passes SIO base addr to SSDT gen
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irq 0x70 = 7
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drq 0x74 = 4 # No DMA
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chip superio/nuvoton/nct6791d
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irq 0xf0 = 0x3c # Printer mode
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device pnp 2e.1 on
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end
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# Global Control Registers
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device pnp 2e.2 on # UART A
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# Device IRQ Polarity
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io 0x60 = 0x03f8
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irq 0x13 = 0x00
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irq 0x70 = 4
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irq 0x14 = 0x00
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end
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# Global Option
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device pnp 2e.3 on # IR
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irq 0x24 = 0xfb
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io 0x60 = 0x02f8
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irq 0x27 = 0x10
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irq 0x70 = 3
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# Multi Function
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end
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irq 0x1a = 0xb0
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device pnp 2e.5 on # PS/2 KBC
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irq 0x1b = 0xe6
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io 0x60 = 0x0060
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irq 0x2a = 0x04
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io 0x62 = 0x0064
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irq 0x2c = 0x40
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irq 0x70 = 1 # Keyboard
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irq 0x2d = 0x03
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irq 0x72 = 12 # Mouse
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end
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# Parallel Port
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device pnp 2e.6 off end # CIR
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io 0x60 = 0x0378
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device pnp 2e.7 on # GPIO6
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irq 0x70 = 7
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irq 0xf6 = 0xff
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drq 0x74 = 4 # No DMA
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irq 0xf7 = 0xff
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irq 0xf0 = 0x3c # Printer mode
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irq 0xf8 = 0xff
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end
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end
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device pnp 2e.2 on # UART A
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device pnp 2e.107 on # GPIO7
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io 0x60 = 0x03f8
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irq 0xe0 = 0x7f
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irq 0x70 = 4
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irq 0xe1 = 0x0d
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end
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end
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device pnp 2e.3 on # IR
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device pnp 2e.207 on # GPIO8
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io 0x60 = 0x02f8
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irq 0xe6 = 0xff
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irq 0x70 = 3
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irq 0xe7 = 0xff
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end
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irq 0xed = 0xff
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device pnp 2e.5 on # PS/2 KBC
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end
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io 0x60 = 0x0060
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device pnp 2e.8 off end # WDT
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io 0x62 = 0x0064
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device pnp 2e.108 on end # GPIO0
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irq 0x70 = 1 # Keyboard
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device pnp 2e.308 off end # GPIO base
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irq 0x72 = 12 # Mouse
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device pnp 2e.408 off end # WDTMEM
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end
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device pnp 2e.708 on end # GPIO1
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device pnp 2e.6 off end # CIR
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device pnp 2e.9 on end # GPIO2
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device pnp 2e.7 on # GPIO6
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device pnp 2e.109 on # GPIO3
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irq 0xf6 = 0xff
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irq 0xe4 = 0x7b
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irq 0xf7 = 0xff
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irq 0xe5 = 0x02
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irq 0xf8 = 0xff
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irq 0xea = 0x04
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end
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end
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device pnp 2e.107 on # GPIO7
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device pnp 2e.209 on # GPIO4
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irq 0xe0 = 0x7f
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irq 0xf0 = 0x7f
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irq 0xe1 = 0x0d
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irq 0xf1 = 0x80
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end
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end
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device pnp 2e.207 on # GPIO8
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device pnp 2e.309 on # GPIO5
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irq 0xe6 = 0xff
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irq 0xf4 = 0xdf
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irq 0xe7 = 0xff
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irq 0xf5 = 0xd5
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irq 0xed = 0xff
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end
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end
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device pnp 2e.a on
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device pnp 2e.8 off end # WDT
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# Power RAM in S3 and let the PCH
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device pnp 2e.108 on end # GPIO0
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# handle power failure actions
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device pnp 2e.308 off end # GPIO base
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irq 0xe4 = 0x70
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device pnp 2e.408 off end # WDTMEM
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# Set HWM reset source to LRESET#
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device pnp 2e.708 on end # GPIO1
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irq 0xe7 = 0x01
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device pnp 2e.9 on end # GPIO2
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end # ACPI
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device pnp 2e.109 on # GPIO3
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device pnp 2e.b on # HWM, LED
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irq 0xe4 = 0x7b
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io 0x60 = 0x0290
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irq 0xe5 = 0x02
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io 0x62 = 0
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irq 0xea = 0x04
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irq 0x70 = 0
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end
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end
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device pnp 2e.209 on # GPIO4
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device pnp 2e.d off end # BCLK, WDT2, WDT_MEM
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irq 0xf0 = 0x7f
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device pnp 2e.e off end # CIR wake-up
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irq 0xf1 = 0x80
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device pnp 2e.f off end # GPIO PP/OD
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end
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device pnp 2e.14 off end # SVID, Port 80 UART
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device pnp 2e.309 on # GPIO5
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device pnp 2e.16 off end # DS5
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irq 0xf4 = 0xdf
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device pnp 2e.116 off end # DS3
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irq 0xf5 = 0xd5
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device pnp 2e.316 on end # PCHDSW
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end
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device pnp 2e.416 off end # DSWWOPT
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device pnp 2e.a on
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device pnp 2e.516 on end # DS3OPT
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# Power RAM in S3 and let the PCH
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device pnp 2e.616 on end # DSDSS
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# handle power failure actions
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device pnp 2e.716 off end # DSPU
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irq 0xe4 = 0x70
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end # superio/nuvoton/nct6791d
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# Set HWM reset source to LRESET#
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irq 0xe7 = 0x01
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end # ACPI
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device pnp 2e.b on # HWM, LED
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io 0x60 = 0x0290
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io 0x62 = 0
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irq 0x70 = 0
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end
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device pnp 2e.d off end # BCLK, WDT2, WDT_MEM
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device pnp 2e.e off end # CIR wake-up
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device pnp 2e.f off end # GPIO PP/OD
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device pnp 2e.14 off end # SVID, Port 80 UART
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device pnp 2e.16 off end # DS5
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device pnp 2e.116 off end # DS3
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device pnp 2e.316 on end # PCHDSW
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device pnp 2e.416 off end # DSWWOPT
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device pnp 2e.516 on end # DS3OPT
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device pnp 2e.616 on end # DSDSS
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device pnp 2e.716 off end # DSPU
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end # chip superio/nuvoton/nct6791d
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end # device pnp 2e.0
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end # chip superio/common
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chip drivers/pc80/tpm
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chip drivers/pc80/tpm
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device pnp 4e.0 on end # TPM module
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device pnp 4e.0 on end # TPM module
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end
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end
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