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mb/asrock/h110m: use SSDT generator for SuperIO 

Modifies the device tree to use the ACPI SSDT generator[1] for NCT6791D
SuperIO, dropping the need to include code from the superio.asl, which
was inherited from another chip (NCT6776) and required fixes. SSDT gen
support for Nuvoton NCT6791D chip was added in the previous patch [2].

[1] https://review.coreboot.org/c/coreboot/+/33033
[2] https://review.coreboot.org/c/coreboot/+/36379

Change-Id: I57b67d10968e5e035536bcb0d8329ce09d50194b
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Maxim Polyakov 2019-10-27 15:07:00 +03:00 committed by Felix Held
parent facbf47224
commit c4f77d943a
2 changed files with 101 additions and 119 deletions
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25
src/mainboard/asrock/h110m/acpi/superio.asl
View File

@ -1,26 +1 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define SUPERIO_DEV SIO0
#define SUPERIO_PNP_BASE 0x2e
#define NCT6776_SHOW_PP
#define NCT6776_SHOW_SP1
#define NCT6776_SHOW_KBC
#define NCT6776_SHOW_HWM
#undef NCT6776_SHOW_GPIO
#include <superio/nuvoton/nct6776/acpi/superio.asl>

11
src/mainboard/asrock/h110m/devicetree.cb
View File

@ -326,8 +326,11 @@ chip soc/intel/skylake
device pci 1e.6 off end # SDCard
device pci 1f.0 on # LPC bridge
subsystemid 0x1849 0x1a43
chip superio/common
device pnp 2e.0 on # passes SIO base addr to SSDT gen
chip superio/nuvoton/nct6791d
device pnp 2e.0 off end # Floppy
device pnp 2e.1 on
# Global Control Registers
# Device IRQ Polarity
@ -420,7 +423,11 @@ chip soc/intel/skylake
device pnp 2e.516 on end # DS3OPT
device pnp 2e.616 on end # DSDSS
device pnp 2e.716 off end # DSPU
end # superio/nuvoton/nct6791d
end # chip superio/nuvoton/nct6791d
end # device pnp 2e.0
end # chip superio/common
chip drivers/pc80/tpm
device pnp 4e.0 on end # TPM module
end