GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

sb/broadcom/bcm5785/early_setup.c: Fix coding style 

Change-Id: Ic8218078f4b1075b41f769e26e34adf9c9b113ac
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Elyes HAOUAS 2018-02-03 00:02:43 +01:00 committed by Felix Held
parent 64e091fc8a
commit c4f897ee3c
1 changed files with 23 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
src/southbridge/broadcom/bcm5785/early_setup.c
View File

@ -27,13 +27,13 @@ static void bcm5785_enable_lpc(void)
/* LPC Control 0 */ /* LPC Control 0 */
byte = pci_read_config8(dev, 0x44); byte = pci_read_config8(dev, 0x44);
/* Serial 0 */ /* Serial 0 */
byte |= (1<<6); byte |= 1 << 6;
pci_write_config8(dev, 0x44, byte); pci_write_config8(dev, 0x44, byte);
/* LPC Control 4 */ /* LPC Control 4 */
byte = pci_read_config8(dev, 0x48); byte = pci_read_config8(dev, 0x48);
/* superio port 0x2e/4e enable */ /* superio port 0x2e/4e enable */
byte |=(1<<1)|(1<<0); byte |= (1 << 1) | (1 << 0);
pci_write_config8(dev, 0x48, byte); pci_write_config8(dev, 0x48, byte);
} }
@ -46,21 +46,19 @@ static void bcm5785_enable_wdt_port_cf9(void)
dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
dword_old = pci_read_config32(dev, 0x4c); dword_old = pci_read_config32(dev, 0x4c);
dword = dword_old | (1<<4); //enable Timer Func dword = dword_old | (1 << 4); //enable Timer Func
if (dword != dword_old ) { if (dword != dword_old)
pci_write_config32(dev, 0x4c, dword); pci_write_config32(dev, 0x4c, dword);
}
dword_old = pci_read_config32(dev, 0x6c); dword_old = pci_read_config32(dev, 0x6c);
dword = dword_old | (1<<9); //unhide Timer Func in pci space dword = dword_old | (1 << 9); //unhide Timer Func in pci space
if (dword != dword_old ) { if (dword != dword_old)
pci_write_config32(dev, 0x6c, dword); pci_write_config32(dev, 0x6c, dword);
}
dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0); dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0);
/* enable cf9 */ /* enable cf9 */
pci_write_config8(dev, 0x40, (1<<2)); pci_write_config8(dev, 0x40, 1 << 2);
} }
unsigned get_sbdn(unsigned bus) unsigned get_sbdn(unsigned bus)
@ -74,7 +72,7 @@ unsigned get_sbdn(unsigned bus)
PCI_ID(0x1166, 0x0036), PCI_ID(0x1166, 0x0036),
bus); bus);
return (dev>>15) & 0x1f; return (dev >> 15) & 0x1f;
} }
@ -84,7 +82,7 @@ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
{ {
//ACPI Decode Enable //ACPI Decode Enable
outb(0x0e, 0xcd6); outb(0x0e, 0xcd6);
outb((1<<3), 0xcd7); outb(1 << 3, 0xcd7);
// set port to 0x2060 // set port to 0x2060
outb(0x67, 0xcd6); outb(0x67, 0xcd6);
@ -138,7 +136,7 @@ static void bcm5785_enable_msg(void)
dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
byte = pci_read_config8(dev, 0x42); byte = pci_read_config8(dev, 0x42);
byte = (1<<1); //enable a20 byte = 1 << 1; //enable a20
pci_write_config8(dev, 0x42, byte); pci_write_config8(dev, 0x42, byte);
dword_old = pci_read_config32(dev, 0x6c); dword_old = pci_read_config32(dev, 0x6c);
@ -148,10 +146,13 @@ static void bcm5785_enable_msg(void)
// bit 2: enable keyboard init message // bit 2: enable keyboard init message
// bit 1: enable upsteam messages // bit 1: enable upsteam messages
// bit 0: enable shutdowm message to init generation // bit 0: enable shutdowm message to init generation
dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor
if (dword != dword_old ) { /* bit 1 and bit 4 must be set, otherwise
* interrupt msg will not be delivered to the processor
*/
dword = dword_old | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
if (dword != dword_old)
pci_write_config32(dev, 0x6c, dword); pci_write_config32(dev, 0x6c, dword);
}
} }
static void bcm5785_early_setup(void) static void bcm5785_early_setup(void)
@ -164,13 +165,13 @@ static void bcm5785_early_setup(void)
// enable device on bcm5785 at first // enable device on bcm5785 at first
dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
dword = pci_read_config32(dev, 0x64); dword = pci_read_config32(dev, 0x64);
dword |= (1<<15) | (1<<11) | (1<<3); // ioapci enable dword |= (1 << 15) | (1 << 11) | (1 << 3); // ioapci enable
dword |= (1<<8); // USB enable dword |= 1 << 8; // USB enable
dword |= /* (1<<27)|*/(1<<14); // IDE enable dword |= /* (1 << 27)|*/ 1 << 14; // IDE enable
pci_write_config32(dev, 0x64, dword); pci_write_config32(dev, 0x64, dword);
byte = pci_read_config8(dev, 0x84); byte = pci_read_config8(dev, 0x84);
byte |= (1<<0); // SATA enable byte |= 1 << 0; // SATA enable
pci_write_config8(dev, 0x84, byte); pci_write_config8(dev, 0x84, byte);
// WDT and cf9 for later in ramstage to call hard_reset // WDT and cf9 for later in ramstage to call hard_reset
@ -182,7 +183,7 @@ static void bcm5785_early_setup(void)
// IDE related // IDE related
//F0 //F0
byte = pci_read_config8(dev, 0x4e); byte = pci_read_config8(dev, 0x4e);
byte |= (1<<4); //enable IDE ext regs byte |= 1 << 4; //enable IDE ext regs
pci_write_config8(dev, 0x4e, byte); pci_write_config8(dev, 0x4e, byte);
//F1 //F1
@ -193,7 +194,7 @@ static void bcm5785_early_setup(void)
pci_write_config8(dev, 0xb0, 0x01); pci_write_config8(dev, 0xb0, 0x01);
pci_write_config8(dev, 0xb2, 0x02); pci_write_config8(dev, 0xb2, 0x02);
byte = pci_read_config8(dev, 0x06); byte = pci_read_config8(dev, 0x06);
byte |= (1<<4); // so b0, b2 can not be changed from now byte |= 1 << 4; // so b0, b2 can not be changed from now
pci_write_config8(dev, 0x06, byte); pci_write_config8(dev, 0x06, byte);
byte = pci_read_config8(dev, 0x49); byte = pci_read_config8(dev, 0x49);
byte |= 1; // enable second channel byte |= 1; // enable second channel
@ -203,7 +204,7 @@ static void bcm5785_early_setup(void)
dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
byte = pci_read_config8(dev, 0x40); byte = pci_read_config8(dev, 0x40);
byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable byte |= (1 << 3) | (1 << 2); // LPC Retry, LPC to PCI DMA enable
pci_write_config8(dev, 0x40, byte); pci_write_config8(dev, 0x40, byte);
pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end