soc/intel/cnl: add panel and backlight configuration code

Add code for panel and backlight configuration.

Tested successfully with libgfxinit on Clevo L141CU.

Change-Id: If619b28478b4b0d18f28f318c16336e0de76e129
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/soc/intel/cannonlake/Makefile.inc

@@ -36,6 +36,7 @@ ramstage-y += cpu.c
 ramstage-y += elog.c
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
+ramstage-y += graphics.c
 ramstage-y += gspi.c
 ramstage-y += i2c.c
 ramstage-y += lockdown.c

src/soc/intel/cannonlake/chip.h

@@ -5,6 +5,7 @@
 
 #include <intelblocks/cfg.h>
 #include <drivers/i2c/designware/dw_i2c.h>
+#include <drivers/intel/gma/gma.h>
 #include <intelblocks/gpio.h>
 #include <intelblocks/gspi.h>
 #include <intelblocks/lpc_lib.h>
@@ -437,6 +438,10 @@ struct soc_intel_cannonlake_config {
 	 * Only override CPU flex ratio if don't want to boot with non-turbo max.
 	 */
 	uint8_t cpu_ratio_override;
+
+	struct i915_gpu_panel_config panel_cfg;
+
+	struct i915_gpu_controller_info gfx;
 };
 
 typedef struct soc_intel_cannonlake_config config_t;

src/soc/intel/cannonlake/graphics.c

@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <commonlib/helpers.h>
+#include <device/device.h>
+#include <device/mmio.h>
+#include <device/pci_def.h>
+#include <device/resource.h>
+#include <drivers/intel/gma/i915_reg.h>
+#include <intelblocks/graphics.h>
+#include <soc/ramstage.h>
+#include <types.h>
+
+void graphics_soc_panel_init(struct device *dev)
+{
+	const struct soc_intel_cannonlake_config *conf = dev->chip_info;
+	const struct i915_gpu_panel_config *panel_cfg;
+	const struct resource *mmio_res;
+	void *mmio;
+	uint32_t reg32;
+	unsigned int pwm_period, pwm_polarity, pwm_duty;
+
+	if (!conf)
+		return;
+
+	panel_cfg = &conf->panel_cfg;
+
+	mmio_res = probe_resource(dev, PCI_BASE_ADDRESS_0);
+	if (!mmio_res || !mmio_res->base)
+		return;
+	mmio = (void *)(uintptr_t)mmio_res->base;
+
+	/* Panel timings */
+
+	reg32 = ((DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f) << 4;
+	reg32 |= PANEL_POWER_RESET;
+	write32(mmio + PCH_PP_CONTROL, reg32);
+
+	reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16;
+	reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff;
+	write32(mmio + PCH_PP_ON_DELAYS, reg32);
+
+	reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16;
+	reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff;
+	write32(mmio + PCH_PP_OFF_DELAYS, reg32);
+
+	/* Backlight */
+	if (panel_cfg->backlight_pwm_hz) {
+		pwm_polarity = panel_cfg->backlight_polarity ? BXT_BLC_PWM_POLARITY : 0;
+		pwm_period = DIV_ROUND_CLOSEST(CONFIG_CPU_XTAL_HZ, panel_cfg->backlight_pwm_hz);
+		pwm_duty = DIV_ROUND_CLOSEST(pwm_period, 2); /* Start with 50 % */
+
+		write32(mmio + BXT_BLC_PWM_FREQ(0), pwm_period);
+		write32(mmio + BXT_BLC_PWM_CTL(0),  pwm_polarity);
+		write32(mmio + BXT_BLC_PWM_DUTY(0), pwm_duty);
+	}
+}
+
+const struct i915_gpu_controller_info *
+intel_igd_get_controller_info(const struct device *const dev)
+{
+	const struct soc_intel_cannonlake_config *const chip = dev->chip_info;
+	return &chip->gfx;
+}