linkb_to_host
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Yinghai Lu
parent
1858844647
commit
c507e4de73
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@ -11,9 +11,9 @@ static inline void print_linkn_in (const char *strval, uint8_t byteval)
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print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n");
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}
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static unsigned ht_lookup_slave_capability(device_t dev)
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static uint8_t ht_lookup_slave_capability(device_t dev)
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{
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unsigned pos;
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uint8_t pos;
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uint8_t hdr_type;
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hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
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@ -44,7 +44,7 @@ static unsigned ht_lookup_slave_capability(device_t dev)
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return pos;
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}
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static void ht_collapse_previous_enumeration(unsigned bus)
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static void ht_collapse_previous_enumeration(uint8_t bus)
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{
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device_t dev;
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uint32_t id;
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@ -62,7 +62,8 @@ static void ht_collapse_previous_enumeration(unsigned bus)
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*/
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for(dev = PCI_DEV(bus, 1, 0); dev <= PCI_DEV(bus, 0x1f, 0x7); dev += PCI_DEV(0, 1, 0)) {
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uint32_t id;
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unsigned pos, flags;
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uint8_t pos;
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uint16_t flags;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if ((id == 0xffffffff) || (id == 0x00000000) ||
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@ -82,10 +83,10 @@ static void ht_collapse_previous_enumeration(unsigned bus)
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}
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}
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static unsigned ht_read_freq_cap(device_t dev, unsigned pos)
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static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos)
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{
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/* Handle bugs in valid hypertransport frequency reporting */
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unsigned freq_cap;
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uint16_t freq_cap;
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uint32_t id;
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freq_cap = pci_read_config16(dev, pos);
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@ -200,8 +201,7 @@ static int ht_optimize_link(
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return needs_reset;
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}
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static int ht_setup_chain(device_t udev, unsigned upos)
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static int ht_setup_chain(device_t udev, uint8_t upos)
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{
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/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
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* On most boards this just happens. If a cpu has multiple
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@ -221,7 +221,9 @@ static int ht_setup_chain(device_t udev, unsigned upos)
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do {
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uint32_t id;
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uint8_t pos;
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unsigned flags, count;
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uint16_t flags, count;
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unsigned offs;
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device_t dev = PCI_DEV(0, 0, 0);
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last_unitid = next_unitid;
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@ -239,8 +241,11 @@ static int ht_setup_chain(device_t udev, unsigned upos)
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break;
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}
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/* get ht direction */
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offs = (pci_read_config16(dev, pos + PCI_CAP_FLAGS) & (1<<10)) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS;
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/* Setup the Hypertransport link */
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reset_needed |= ht_optimize_link(udev, upos, uoffs, dev, pos, PCI_HT_SLAVE0_OFFS);
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reset_needed |= ht_optimize_link(udev, upos, uoffs, dev, pos, offs);
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/* Update the Unitid of the current device */
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flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
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@ -251,7 +256,7 @@ static int ht_setup_chain(device_t udev, unsigned upos)
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/* Remeber the location of the last device */
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udev = PCI_DEV(0, next_unitid, 0);
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upos = pos;
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uoffs = PCI_HT_SLAVE1_OFFS;
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uoffs = (offs != PCI_HT_SLAVE0_OFFS) ? PCI_HT_SLAVE0_OFFS : PCI_HT_SLAVE1_OFFS;
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/* Compute the number of unitids consumed */
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count = (flags >> 5) & 0x1f;
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@ -261,7 +266,7 @@ static int ht_setup_chain(device_t udev, unsigned upos)
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return reset_needed;
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}
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static int ht_setup_chainx(device_t udev, unsigned upos, unsigned bus)
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static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus)
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{
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unsigned next_unitid, last_unitid;
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unsigned uoffs;
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@ -273,7 +278,8 @@ static int ht_setup_chainx(device_t udev, unsigned upos, unsigned bus)
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do {
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uint32_t id;
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uint8_t pos;
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unsigned flags, count;
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uint16_t flags, count;
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unsigned offs;
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device_t dev = PCI_DEV(bus, 0, 0);
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last_unitid = next_unitid;
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@ -292,8 +298,11 @@ static int ht_setup_chainx(device_t udev, unsigned upos, unsigned bus)
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break;
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}
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/* get ht direction */
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offs = (pci_read_config16(dev, pos + PCI_CAP_FLAGS) & (1<<10)) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS;
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/* Setup the Hypertransport link */
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reset_needed |= ht_optimize_link(udev, upos, uoffs, dev, pos, PCI_HT_SLAVE0_OFFS);
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reset_needed |= ht_optimize_link(udev, upos, uoffs, dev, pos, offs);
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/* Update the Unitid of the current device */
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flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
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@ -304,7 +313,7 @@ static int ht_setup_chainx(device_t udev, unsigned upos, unsigned bus)
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/* Remeber the location of the last device */
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udev = PCI_DEV(bus, next_unitid, 0);
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upos = pos;
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uoffs = PCI_HT_SLAVE1_OFFS;
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uoffs = ( offs != PCI_HT_SLAVE0_OFFS ) ? PCI_HT_SLAVE0_OFFS : PCI_HT_SLAVE1_OFFS;
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/* Compute the number of unitids consumed */
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count = (flags >> 5) & 0x1f;
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@ -314,7 +323,7 @@ static int ht_setup_chainx(device_t udev, unsigned upos, unsigned bus)
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return reset_needed;
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}
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static int optimize_link_read_pointer(unsigned node, unsigned linkn, uint8_t linkt, unsigned val)
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static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt, uint8_t val)
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{
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uint32_t dword, dword_old;
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uint8_t link_type;
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@ -338,18 +347,18 @@ static int optimize_link_read_pointer(unsigned node, unsigned linkn, uint8_t lin
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return 0;
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}
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static int optimize_link_in_coherent(int ht_c_num)
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static int optimize_link_in_coherent(uint8_t ht_c_num)
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{
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int reset_needed;
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int i;
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uint8_t i;
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reset_needed = 0;
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for (i = 0; i < ht_c_num; i++) {
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uint32_t reg;
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unsigned nodeid, linkn;
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unsigned busn;
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unsigned val;
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uint8_t nodeid, linkn;
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uint8_t busn;
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uint8_t val;
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reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
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@ -373,7 +382,7 @@ static int optimize_link_in_coherent(int ht_c_num)
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return reset_needed;
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}
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static int ht_setup_chains(int ht_c_num)
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static int ht_setup_chains(uint8_t ht_c_num)
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{
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/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
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* On most boards this just happens. If a cpu has multiple
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@ -381,18 +390,18 @@ static int ht_setup_chains(int ht_c_num)
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* links needs to be programed to point at bus 0.
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*/
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int reset_needed;
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unsigned upos;
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uint8_t upos;
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device_t udev;
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int i;
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uint8_t i;
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reset_needed = 0;
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for (i = 0; i < ht_c_num; i++) {
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uint32_t reg;
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unsigned devpos;
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uint8_t devpos;
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unsigned regpos;
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uint32_t dword;
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unsigned busn;
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uint8_t busn;
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reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
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@ -412,7 +421,8 @@ static int ht_setup_chains(int ht_c_num)
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upos = ((reg & 0xf00)>>8) * 0x20 + 0x80;
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udev = PCI_DEV(0, devpos, 0);
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reset_needed |= ht_setup_chainx(udev,upos,busn );
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reset_needed |= ht_setup_chainx(udev,upos,busn);
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}
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@ -423,12 +433,12 @@ static int ht_setup_chains(int ht_c_num)
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static int ht_setup_chains_x(void)
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{
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int nodeid;
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uint8_t nodeid;
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uint32_t reg;
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uint32_t tempreg;
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unsigned next_busn;
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int ht_c_num;
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int nodes;
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uint8_t next_busn;
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uint8_t ht_c_num;
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uint8_t nodes;
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/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
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reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
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@ -447,14 +457,14 @@ static int ht_setup_chains_x(void)
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for(nodeid=0; nodeid<nodes; nodeid++) {
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device_t dev;
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unsigned linkn;
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uint8_t linkn;
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dev = PCI_DEV(0, 0x18+nodeid,0);
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for(linkn = 0; linkn<3; linkn++) {
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unsigned regpos;
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regpos = 0x98 + 0x20 * linkn;
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reg = pci_read_config32(dev, regpos);
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if ((reg & 0x17) != 7) continue; /* it is not non conherent or not connected*/
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print_linkn_in("NC node/link=", ((nodeid & 0xf)<<4)|(linkn & 0xf));
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print_linkn_in("NC node|link=", ((nodeid & 0xf)<<4)|(linkn & 0xf));
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tempreg = 3 | (nodeid <<4) | (linkn<<8);
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/*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */
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for(ht_c_num=0;ht_c_num<4; ht_c_num++) {
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@ -488,7 +498,7 @@ static int ht_setup_chains_x(void)
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}
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/* recount ht_c_num*/
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int i=0;
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uint8_t i=0;
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for(ht_c_num=0;ht_c_num<4; ht_c_num++) {
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reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4);
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if(((reg & 0xf) != 0x0)) {
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