diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c
index d40db7bda3..5ec6f30459 100644
--- a/src/mainboard/msi/ms9185/mptable.c
+++ b/src/mainboard/msi/ms9185/mptable.c
@@ -43,8 +43,8 @@ extern void get_bus_conf(void);
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[3] = "MSI";
-        static const char productid[6] = "MS9185       ";
+        static const char oem[8] = "MSI     ";
+        static const char productid[12] = "MS9185      ";
         struct mp_config_table *mc;
 
         unsigned char bus_num;
@@ -82,8 +82,7 @@ static void *smp_write_config_table(void *v)
 
 /*I/O APICs:   APIC ID Version State           Address*/
         {
-                device_t dev = 0;
-               int i;
+		device_t dev = 0;
                struct resource *res;
                for(i=0; i<3; i++) {
                        dev = dev_find_device(0x1166, 0x0235, dev);
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index 04c8dbd540..e7fb87227f 100644
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -57,6 +57,7 @@
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
+#include <reset.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
@@ -151,7 +152,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        };
 
-       struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
+		CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         int needs_reset;
         unsigned bsp_apicid = 0;
diff --git a/src/mainboard/via/epia-m/fadt.c b/src/mainboard/via/epia-m/fadt.c
index 632dbf6df8..d1af915d7b 100644
--- a/src/mainboard/via/epia-m/fadt.c
+++ b/src/mainboard/via/epia-m/fadt.c
@@ -37,8 +37,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 	memcpy(header->asl_compiler_id,ASLC,4);
 	header->asl_compiler_revision=0;
 
-	fadt->firmware_ctrl=facs;
-	fadt->dsdt= dsdt;
+	fadt->firmware_ctrl=(u32)facs;
+	fadt->dsdt=(u32)dsdt;
 	fadt->preferred_pm_profile=0;
 	fadt->sci_int=5;
 	fadt->smi_cmd = 0;
@@ -84,9 +84,9 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 	fadt->reset_reg.addrh = 0x0;
 
 	fadt->reset_value = 0;
-	fadt->x_firmware_ctl_l = facs;
+	fadt->x_firmware_ctl_l = (u32)facs;
 	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = dsdt;
+	fadt->x_dsdt_l = (u32)dsdt;
 	fadt->x_dsdt_h = 0;
 
 	fadt->x_pm1a_evt_blk.space_id = 1;
diff --git a/src/mainboard/via/epia-m/mainboard.c b/src/mainboard/via/epia-m/mainboard.c
index 0fe49fc46f..43e11d30ba 100644
--- a/src/mainboard/via/epia-m/mainboard.c
+++ b/src/mainboard/via/epia-m/mainboard.c
@@ -7,9 +7,6 @@
 #include "chip.h"
 #include "vgachip.h"
 
-void vga_enable_console();
-
-
 static void vga_fixup(void) {
         // we do this right here because:
         // - all the hardware is working, and some VGA bioses seem to need
@@ -22,8 +19,6 @@ static void vga_fixup(void) {
         do_vgabios();
         post_code(0x93);
 	vga_enable_console();
-
-
 }
  
 void write_protect_vgabios(void)
diff --git a/src/mainboard/via/epia-n/acpi_tables.c b/src/mainboard/via/epia-n/acpi_tables.c
index 904ddefb07..0f194de34f 100644
--- a/src/mainboard/via/epia-n/acpi_tables.c
+++ b/src/mainboard/via/epia-n/acpi_tables.c
@@ -126,7 +126,6 @@ unsigned long write_acpi_tables(unsigned long start)
 	unsigned long current;
 	acpi_rsdp_t *rsdp;
 	acpi_rsdt_t *rsdt;
-	acpi_xsdt_t *xsdt;
 	acpi_madt_t *madt;
 	acpi_fadt_t *fadt;
 	acpi_facs_t *facs;
@@ -163,8 +162,10 @@ unsigned long write_acpi_tables(unsigned long start)
 	dsdt = (acpi_header_t *)current;
 	current += AmlCode.length;
 	memcpy((void *)dsdt, &AmlCode, AmlCode.length);
+#if 0
 	dsdt->checksum = 0; // don't trust intel iasl compiler to get this right
 	dsdt->checksum = acpi_checksum(dsdt,dsdt->length);
+#endif
 	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n",dsdt,dsdt->length);
 	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
 
diff --git a/src/mainboard/via/epia-n/fadt.c b/src/mainboard/via/epia-n/fadt.c
index f894eee55d..d7896f5cb8 100644
--- a/src/mainboard/via/epia-n/fadt.c
+++ b/src/mainboard/via/epia-n/fadt.c
@@ -39,8 +39,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 	memcpy(header->asl_compiler_id,ASLC,4);
 	header->asl_compiler_revision=0;
 
-	fadt->firmware_ctrl=facs;
-	fadt->dsdt= dsdt;
+	fadt->firmware_ctrl=(u32)facs;
+	fadt->dsdt= (u32)dsdt;
 	fadt->preferred_pm_profile=0;
 	fadt->sci_int=VT8237R_ACPI_IRQ;
 	fadt->smi_cmd = 0;
@@ -86,9 +86,9 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 	fadt->reset_reg.addrh = 0x0;
 
 	fadt->reset_value = 0;
-	fadt->x_firmware_ctl_l = facs;
+	fadt->x_firmware_ctl_l = (u32)facs;
 	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = dsdt;
+	fadt->x_dsdt_l = (u32)dsdt;
 	fadt->x_dsdt_h = 0;
 
 	fadt->x_pm1a_evt_blk.space_id = 1;
diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c
index 0d6d743750..31daa68b51 100644
--- a/src/northbridge/amd/amdfam10/setup_resource_map.c
+++ b/src/northbridge/amd/amdfam10/setup_resource_map.c
@@ -195,6 +195,7 @@ static void setup_resource_map_x(const u32 *register_values, u32 max)
 #endif
 }
 
+#if 0
 static void setup_iob_resource_map(const u32 *register_values, u32 max)
 {
 	u32 i;
@@ -227,5 +228,5 @@ static void setup_io_resource_map(const u32 *register_values, u32 max)
 		outl(reg, where);
 	}
 }
-
+#endif
 
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index 6a85516211..b4e3d64d63 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -444,7 +444,6 @@ end_of_chain: ;
 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
 	if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used ) {
 		uint16_t flags;
-		int i;
 		flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
 		flags &= ~0x1f;
 		flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
@@ -452,6 +451,7 @@ end_of_chain: ;
 
 		#if RAMINIT_SYSINFO == 1
 		// Here need to change the dev in the array
+		int i;
 		for(i=0;i<sysinfo->link_pair_num;i++)
 		{
 			struct link_pair_st *link_pair = &sysinfo->link_pair[i];
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index cac9f80097..eaeff9ee9c 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -33,7 +33,7 @@
 #define QRANK_DIMM_SUPPORT 0
 #endif
 
-#if DEBUG_RAM_SETUP
+#if CONFIG_DEBUG_RAM_SETUP
 #define printk_raminit(fmt, arg...) printk(BIOS_DEBUG, fmt, arg)
 #else
 #define printk_raminit(fmt, arg...)
diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c
index ec3c0cf919..96f1c5dca6 100644
--- a/src/northbridge/amd/amdk8/setup_resource_map.c
+++ b/src/northbridge/amd/amdk8/setup_resource_map.c
@@ -192,6 +192,7 @@ static void setup_resource_map_x(const unsigned int *register_values, int max)
 #endif
 }
 
+#if 0
 static void setup_iob_resource_map(const unsigned int *register_values, int max)
 {
 	int i;
@@ -267,7 +268,6 @@ static void setup_io_resource_map(const unsigned int *register_values, int max)
 	}
 }
 
-#if 0
 static void setup_mem_resource_map(const unsigned int *register_values, int max)
 {
 	int i;
diff --git a/src/northbridge/via/cn400/cn400.h b/src/northbridge/via/cn400/cn400.h
index 3c9e8fd52a..baa58a1206 100644
--- a/src/northbridge/via/cn400/cn400.h
+++ b/src/northbridge/via/cn400/cn400.h
@@ -19,7 +19,8 @@
  */
 
 #ifndef __PRE_RAM__
-static void cn400_noop(void)
+// HACK
+static inline void cn400_noop(device_t dev)
 {
 }
 #endif
diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c
index 5aec00835f..f867427824 100644
--- a/src/northbridge/via/cn400/northbridge.c
+++ b/src/northbridge/via/cn400/northbridge.c
@@ -238,7 +238,7 @@ static void cn400_domain_set_resources(device_t dev)
 	if (mc_dev) {
 		unsigned long tomk, tolmk;
 		unsigned char rambits;
-		int i, idx;
+		int idx;
 
 		rambits = pci_read_config8(mc_dev, 0x47);
 		tomk = rambits * 32 * 1024;
diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c
index 3144395180..7d33e44236 100644
--- a/src/northbridge/via/vt8623/northbridge.c
+++ b/src/northbridge/via/vt8623/northbridge.c
@@ -105,7 +105,7 @@ static const struct pci_driver agp_driver __pci_driver = {
 static void vga_init(device_t dev)
 {
 //	unsigned long fb;
-	msr_t clocks1,clocks2,instructions,setup;
+	//msr_t clocks1,clocks2,instructions,setup;
 
 	printk(BIOS_DEBUG, "VGA random fixup ...\n");
 	pci_write_config8(dev, 0x04, 0x07);
diff --git a/src/northbridge/via/vt8623/raminit.c b/src/northbridge/via/vt8623/raminit.c
index 40338dae7e..f57127b3da 100644
--- a/src/northbridge/via/vt8623/raminit.c
+++ b/src/northbridge/via/vt8623/raminit.c
@@ -69,7 +69,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 {
 	device_t north = (device_t) 0;
 	uint8_t b, c, bank;
-	uint16_t i,j;
+	uint16_t i;
 	unsigned long bank_address;
 
 	print_debug("vt8623 init starting\n");
diff --git a/src/northbridge/via/vx800/vx800.h b/src/northbridge/via/vx800/vx800.h
index 5e1c4df205..1d832508ac 100644
--- a/src/northbridge/via/vx800/vx800.h
+++ b/src/northbridge/via/vx800/vx800.h
@@ -21,7 +21,7 @@
 #define  VX800_H 1
 
 #ifndef __PRE_RAM__
-static void vx800_noop()
+static inline void vx800_noop(device_t dev)
 {
 }
 #endif
diff --git a/src/northbridge/via/vx800/vx800_ide.c b/src/northbridge/via/vx800/vx800_ide.c
index b3d6bc2c02..b4c40d4e2f 100644
--- a/src/northbridge/via/vx800/vx800_ide.c
+++ b/src/northbridge/via/vx800/vx800_ide.c
@@ -166,13 +166,10 @@ static const idedevicepcitable[16 * 12] = {
 
 static void ide_init(struct device *dev)
 {
-	uint8_t enables, Rx89, RxC0;
 	u8 i, data;
-	struct ATA_REG_INIT_TABLE *pEntry;
 	printk(BIOS_INFO, "ide_init\n");
 
-#if 1
-	/*these 3 lines help to keep interl back door for DID VID SUBID untouched */
+	/* these 3 lines help to keep interl back door for DID VID SUBID untouched */
 	u16 data16_1, data16_2;
 	data16_1 = pci_read_config16(dev, 0xba);
 	data16_2 = pci_read_config16(dev, 0xbe);
@@ -189,7 +186,7 @@ static void ide_init(struct device *dev)
 	//these 2 lines help to keep interl back door for DID VID SUBID untouched
 	pci_write_config16(dev, 0xba, data16_1);
 	pci_write_config16(dev, 0xbe, data16_2);
-#endif
+
 	/* Force interrupts to use compat mode. */
 	pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0);
 	pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff);
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c
index 7eb4e607c7..3ac28e59ca 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785.c
@@ -12,8 +12,7 @@ void bcm5785_enable(device_t dev)
 {
 	device_t sb_pci_main_dev;
 	device_t bus_dev;
-	unsigned index;
-	unsigned reg_old, reg;
+	// unsigned index;
 
 	/* See if we are on the behind the pcix bridge */
 	bus_dev = dev->bus->dev;
@@ -23,18 +22,17 @@ void bcm5785_enable(device_t dev)
 		unsigned devfn;
 		devfn = bus_dev->path.pci.devfn + (1 << 3);
 		sb_pci_main_dev = dev_find_slot(bus_dev->bus->secondary, devfn);
-//		index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
+		// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
 	} else if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
                 (bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X )
         {
                 unsigned devfn;
                 devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3);
                 sb_pci_main_dev = dev_find_slot(bus_dev->bus->dev->bus->secondary, devfn);
-//                index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
+		// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
         }
 	else { // same bus
 		unsigned devfn;
-		uint32_t id;
 		devfn = (dev->path.pci.devfn) & ~7;
 		if( dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) { 
 			if(dev->device == 0x0036) //PCI-X Bridge
@@ -43,7 +41,7 @@ void bcm5785_enable(device_t dev)
 			{ devfn -= (1<<3); }
 		}
 		sb_pci_main_dev = dev_find_slot(dev->bus->secondary, devfn);
-//		index = dev->path.pci.devfn & 7;
+		// index = dev->path.pci.devfn & 7;
 	}
 	if (!sb_pci_main_dev) {
 		return;
@@ -51,6 +49,7 @@ void bcm5785_enable(device_t dev)
 
 	// get index now
 #if 0
+	unsigned reg_old, reg;
 	if (index < 16) {
 		reg = reg_old = pci_read_config16(sb_pci_main_dev, 0x48);
 		reg &= ~(1 << index);
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
index 66b270cdff..25ad7baf32 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
@@ -6,8 +6,6 @@
 static void bcm5785_enable_rom(void)
 {
         unsigned char byte;
-        uint32_t dword;
-        uint16_t word;
         device_t addr;
 
         /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
@@ -109,7 +107,7 @@ static void ldtstop_sb(void)
 }
 
 
-static void hard_reset(void)
+void hard_reset(void)
 {
         bcm5785_enable_wdt_port_cf9();
 
@@ -120,7 +118,7 @@ static void hard_reset(void)
         outb(0x0e, 0x0cf9);
 }
 
-static void soft_reset(void)
+void soft_reset(void)
 {
         bcm5785_enable_wdt_port_cf9();
 
@@ -164,7 +162,6 @@ static void bcm5785_enable_msg(void)
 static void bcm5785_early_setup(void)
 {
         uint8_t byte;
-        uint16_t word;
         uint32_t dword;
         device_t dev;
 
@@ -181,13 +178,12 @@ static void bcm5785_early_setup(void)
         byte |= (1<<0); // SATA enable
         pci_write_config8(dev, 0x84, byte);
 
-// wdt and cf9 for later in coreboot_ram to call hard_reset
+// WDT and cf9 for later in coreboot_ram to call hard_reset
         bcm5785_enable_wdt_port_cf9();
 
         bcm5785_enable_msg();
 
 
-#if 1
 // IDE related
 	//F0
         byte = pci_read_config8(dev, 0x4e);
@@ -207,9 +203,8 @@ static void bcm5785_early_setup(void)
         byte = pci_read_config8(dev, 0x49);
         byte |= 1; // enable second channel
         pci_write_config8(dev, 0x49, byte);
-#endif
 
-//F2
+	//F2
         dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
 
         byte = pci_read_config8(dev, 0x40);
@@ -218,7 +213,6 @@ static void bcm5785_early_setup(void)
 
         pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end
 
-#if 1
 // USB related
         pci_write_config8(dev, 0x90, 0x40);
         pci_write_config8(dev, 0x92, 0x06);
@@ -227,5 +221,4 @@ static void bcm5785_early_setup(void)
         pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func
         pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func
         pci_write_config8(dev, 0xb4, 0x40);
-#endif
 }
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_ide.c b/src/southbridge/broadcom/bcm5785/bcm5785_ide.c
index 82263e8ec5..90a41680f6 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_ide.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785_ide.c
@@ -12,9 +12,6 @@
 
 static void bcm5785_ide_read_resources(device_t dev)
 {
-        struct resource *res;
-        unsigned long index;
-
         /* Get the normal pci resources of this device */
         pci_dev_read_resources(dev);
 
@@ -26,9 +23,6 @@ static void bcm5785_ide_read_resources(device_t dev)
 
 static void ide_init(struct device *dev)
 {
-	uint16_t word;
-
-
 }
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
@@ -36,6 +30,7 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
         pci_write_config32(dev, 0x40,
                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
+
 static struct pci_operations lops_pci = {
         .set_subsystem = lpci_set_subsystem,
 };
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
index 462d9edf2d..e76dd3a45a 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
@@ -70,7 +70,6 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
         unsigned link; 
 	uint32_t reg;
 	int i;
-	int var_num = 0;
 	
 	reg = pci_read_config8(dev, 0x44);
 
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_reset.c b/src/southbridge/broadcom/bcm5785/bcm5785_reset.c
index b6fc5926b3..6e05e93711 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_reset.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785_reset.c
@@ -4,6 +4,7 @@
  */
 
 #include <arch/io.h>
+#include <reset.h>
 
 #define PCI_DEV(BUS, DEV, FN) ( \
         (((BUS) & 0xFFF) << 20) | \
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c b/src/southbridge/broadcom/bcm5785/bcm5785_sata.c
index e82fa3ca8e..ec92ecf7e9 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785_sata.c
@@ -12,17 +12,13 @@
 #include <arch/io.h>
 #include "bcm5785.h"
 
-
 static void sata_init(struct device *dev)
 {
-
 	uint8_t byte;
 
-        uint8_t *base;
-	uint8_t *mmio;
+	u32 mmio;
         struct resource *res;
-        unsigned int mmio_base;
-        volatile unsigned int *mmio_reg;
+        u32 mmio_base;
 	int i;
 
 	if(!(dev->path.pci.devfn & 7)) { // only set it in Func0
@@ -31,27 +27,24 @@ static void sata_init(struct device *dev)
         	pci_write_config8(dev, 0x78, byte);
 
 	        res = find_resource(dev, 0x24);
-	        base = res->base;
-
-                mmio_base = base;
+                mmio_base = res->base;
                 mmio_base &= 0xfffffffc;
-                mmio_reg = (unsigned int *)( mmio_base + 0x10f0 );
-                * mmio_reg = 0x40000001;
-                mmio_reg = ( unsigned int *)( mmio_base + 0x8c );
-                * mmio_reg = 0x00ff2007;
+
+		write32(mmio_base + 0x10f0, 0x40000001);
+		write32(mmio_base + 0x8c, 0x00ff2007);
                 mdelay( 10 );
-                * mmio_reg = 0x78592009;
+		write32(mmio_base + 0x8c, 0x78592009);
                 mdelay( 10 );
-                * mmio_reg = 0x00082004;
+		write32(mmio_base + 0x8c, 0x00082004);
                 mdelay( 10 );
-                * mmio_reg = 0x00002004;
+		write32(mmio_base + 0x8c, 0x00002004);
                 mdelay( 10 );
 
 		//init PHY
 
 		printk(BIOS_DEBUG, "init PHY...\n");
 		for(i=0; i<4; i++) {
-			mmio = base + 0x100 * i; 
+			mmio = res->base + 0x100 * i; 
 			byte = read8(mmio + 0x40);
 			printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte);
 			if(byte & 0x4) {// bit 2 is set
@@ -62,10 +55,7 @@ static void sata_init(struct device *dev)
 	                        printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte);
 			}
 		}
-		
 	}
-
-
 }
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c b/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
index 69e077ebb0..a13e9f3fd0 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
@@ -25,8 +25,6 @@ static void sb_init(device_t dev)
 	uint8_t byte_old;
 	int nmi_option;
 
-	uint32_t dword;
-
 	/* Set up NMI on errors */
 	byte = inb(0x70); // RTC70
 	byte_old = byte;
@@ -47,7 +45,6 @@ static void sb_init(device_t dev)
 static void bcm5785_sb_read_resources(device_t dev)
 {
 	struct resource *res;
-	unsigned long index;
 
 	/* Get the normal pci resources of this device */
 	pci_dev_read_resources(dev); 		
@@ -64,6 +61,7 @@ static void bcm5785_sb_read_resources(device_t dev)
         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 
 }
+
 static int lsmbus_recv_byte(device_t dev)
 {
         unsigned device;
diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c
index a9fcac6ab0..c276389bf7 100644
--- a/src/southbridge/ricoh/rl5c476/rl5c476.c
+++ b/src/southbridge/ricoh/rl5c476/rl5c476.c
@@ -162,7 +162,7 @@ static void rl5c476_init(device_t dev)
 	*cptr = 0x41;
 }
 
-void rl5c476_read_resources(device_t dev)
+static void rl5c476_read_resources(device_t dev)
 {
 
 	struct resource *resource;
@@ -181,7 +181,7 @@ void rl5c476_read_resources(device_t dev)
 	cardbus_read_resources(dev);
 }
 
-void rl5c476_set_resources(device_t dev)
+static void rl5c476_set_resources(device_t dev)
 {
 	struct resource *resource;
 	printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev));
@@ -212,12 +212,10 @@ static const struct pci_driver ricoh_rl5c476_driver __pci_driver = {
 	.device = PCI_DEVICE_ID_RICOH_RL5C476,
 };
 
-void southbridge_init(device_t dev)
+static void southbridge_init(device_t dev)
 {
-
 	struct southbridge_ricoh_rl5c476_config *conf = dev->chip_info;
 	enable_cf_boot = conf->enable_cf;
-
 }
 
 struct chip_operations southbridge_ricoh_rl5c476_ops = {
diff --git a/src/southbridge/via/vt8235/vt8235.c b/src/southbridge/via/vt8235/vt8235.c
index 228da0f948..2687972afa 100644
--- a/src/southbridge/via/vt8235/vt8235.c
+++ b/src/southbridge/via/vt8235/vt8235.c
@@ -10,7 +10,6 @@
 /*
  * Base VT8235.
  */
-static int enabled = 0;
 
 void hard_reset(void) 
 {
@@ -53,11 +52,9 @@ void set_led()
 
 static void vt8235_enable(struct device *dev)
 {
-	struct southbridge_via_vt8235_config *conf = dev->chip_info;
 	unsigned char regval;
 	unsigned short vendor,model;
 
-
 	vendor = pci_read_config16(dev,0);
 	model = pci_read_config16(dev,0x2);
 
@@ -72,7 +69,6 @@ static void vt8235_enable(struct device *dev)
 
 	printk(BIOS_DEBUG, "Initialising Devices\n");
 
-
 	setup_i8259();   // make sure interupt controller is configured before keyboard init 
 
 	/* enable RTC and ethernet */
@@ -87,8 +83,6 @@ static void vt8235_enable(struct device *dev)
    	regval = pci_read_config8(dev, 0x50);
 	regval &= ~(0x36);
 	pci_write_config8(dev, 0x50, regval);
-
-
 }
 
 struct chip_operations southbridge_via_vt8235_ops = {
diff --git a/src/southbridge/via/vt8235/vt8235_lpc.c b/src/southbridge/via/vt8235/vt8235_lpc.c
index 92ba973661..0746bc9a13 100644
--- a/src/southbridge/via/vt8235/vt8235_lpc.c
+++ b/src/southbridge/via/vt8235/vt8235_lpc.c
@@ -105,9 +105,8 @@ static void pci_routing_fixup(struct device *dev)
  * can't figure out how to do !!!!
  */ 
 
-void setup_pm(device_t dev)
+static void setup_pm(device_t dev)
 {
-
 	// Set gen config 0
 	pci_write_config8(dev, 0x80, 0x20);
 
@@ -216,7 +215,7 @@ static void vt8235_init(struct device *dev)
 
 /* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this
    device has a resource to set - so set a dummy one */
-void vt8235_read_resources(device_t dev)
+static void vt8235_read_resources(device_t dev)
 {
 	struct resource *res;
 
@@ -234,21 +233,20 @@ void vt8235_read_resources(device_t dev)
 	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
-void vt8235_set_resources(device_t dev)
+static void vt8235_set_resources(device_t dev)
 {
-	struct resource *resource;
+	//struct resource *resource;
 	//resource = find_resource(dev,1);
 	//resource->flags |= IORESOURCE_STORED;
 	pci_dev_set_resources(dev);
 }
 
-void vt8235_enable_resources(device_t dev)
+static void vt8235_enable_resources(device_t dev)
 {
 	/* vt8235 is not a pci bridge and has no resources of its own (other than standard PC i/o addresses)
            however it does control the isa bus and so we need to manually call enable childrens resources on that bus */
 	pci_dev_enable_resources(dev);
 	enable_childrens_resources(dev);
-
 }
 	
 static void southbridge_init(struct device *dev)
diff --git a/src/southbridge/via/vt8235/vt8235_usb.c b/src/southbridge/via/vt8235/vt8235_usb.c
index 8b2a685807..c712136c72 100644
--- a/src/southbridge/via/vt8235/vt8235_usb.c
+++ b/src/southbridge/via/vt8235/vt8235_usb.c
@@ -27,7 +27,6 @@ static void usb_init(struct device *dev)
 	 */
 }
 
-/*
 static struct device_operations usb_ops = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
@@ -42,4 +41,4 @@ static const struct pci_driver northbridge_driver __pci_driver = {
 	.vendor = PCI_VENDOR_ID_VIA,
 	.device = PCI_DEVICE_ID_VIA_82C586_2,
 };
-*/
+
diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c
index f47c8c8dff..f7acb75766 100644
--- a/src/southbridge/via/vt8237r/vt8237r_lpc.c
+++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c
@@ -65,7 +65,6 @@ static void pci_routing_fixup(struct device *dev)
 {
 #if CONFIG_EPIA_VT8237R_INIT
 	device_t pdev;
-	u8 reg;
 #endif
 
 	/* PCI PNP Interrupt Routing INTE/F - disable */