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soc/intel/skylake: Select common P2SB code 

This patch select CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB to include
common p2sb code block.

BUG=b:78109109
BRANCH=none
TEST=Build and boot EVE.

Change-Id: I3f6aa6398e409a05a35766fb7aeb3aa221dd3970
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26165
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2018-05-08 11:58:01 +05:30
parent cea7e8bdef
commit c51df93ccf
3 changed files with 24 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/intel/skylake/Kconfig
View File

@ -71,6 +71,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_ITSS
select SOC_INTEL_COMMON_BLOCK_LPC
select SOC_INTEL_COMMON_BLOCK_LPSS
select SOC_INTEL_COMMON_BLOCK_P2SB
select SOC_INTEL_COMMON_BLOCK_PCIE
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_PMC

42
src/soc/intel/skylake/finalize.c
View File

@ -22,6 +22,7 @@
#include <cpu/x86/smm.h>
#include <device/pci.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/p2sb.h>
#include <intelblocks/pcr.h>
#include <reg_script.h>
#include <spi-generic.h>
@ -39,7 +40,8 @@
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8)
static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask)
static void pch_configure_endpoints(struct device *dev, int epmask_id,
uint32_t mask)
{
uint32_t reg32;
@ -47,14 +49,11 @@ static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask)
pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask);
}
static void disable_sideband_access(void)
static void disable_sideband_access(struct device *dev)
{
device_t dev;
u8 reg8;
uint32_t mask;
dev = PCH_DEV_P2SB;
/*
* Set p2sb PCI offset EPMASK5 C4h [29, 28, 27, 26] to disable Sideband
* access for PCI Root Bridge.
@ -77,12 +76,12 @@ static void disable_sideband_access(void)
pci_write_config8(dev, PCH_P2SB_E0 + 2, reg8 | (1 << 1));
/* hide p2sb device */
pci_write_config8(dev, PCH_P2SB_E0 + 1, 1);
p2sb_hide();
}
static void pch_disable_heci(void)
{
device_t dev = PCH_DEV_P2SB;
struct device *dev = PCH_DEV_P2SB;
/*
* if p2sb device 1f.1 is not present or hidden in devicetree
@ -92,18 +91,17 @@ static void pch_disable_heci(void)
return;
/* unhide p2sb device */
pci_write_config8(dev, PCH_P2SB_E0 + 1, 0);
p2sb_unhide();
/* disable heci */
pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN,
PCR_PSFX_T0_SHDW_PCIEN_FUNDIS);
disable_sideband_access();
disable_sideband_access(dev);
}
static void pch_finalize_script(void)
static void pch_finalize_script(struct device *dev)
{
device_t dev;
uint32_t reg32;
uint8_t *pmcbase;
config_t *config;
@ -112,7 +110,6 @@ static void pch_finalize_script(void)
/* Display me status before we hide it */
intel_me_status();
dev = PCH_DEV_PMC;
pmcbase = pmc_mmio_regs();
config = dev->chip_info;
@ -150,18 +147,11 @@ static void pch_finalize_script(void)
pch_disable_heci();
}
static void soc_lockdown(void)
static void soc_lockdown(struct device *dev)
{
struct soc_intel_skylake_config *config;
struct device *dev;
u8 reg8;
dev = PCH_DEV_PMC;
/* Check if PMC is enabled, else return */
if (dev == NULL || dev->chip_info == NULL)
return;
config = dev->chip_info;
/* Global SMI Lock */
@ -174,11 +164,19 @@ static void soc_lockdown(void)
static void soc_finalize(void *unused)
{
struct device *dev;
dev = PCH_DEV_PMC;
/* Check if PMC is enabled, else return */
if (dev == NULL || dev->chip_info == NULL)
return;
printk(BIOS_DEBUG, "Finalizing chipset.\n");
pch_finalize_script();
pch_finalize_script(dev);
soc_lockdown();
soc_lockdown(dev);
printk(BIOS_DEBUG, "Finalizing SMM.\n");
outb(APM_CNT_FINALIZE, APM_CNT);

3
src/soc/intel/skylake/include/soc/iomap.h
View File

@ -90,4 +90,7 @@
#define TCO_BASE_ADDDRESS 0x400
#define TCO_BASE_SIZE 0x20
#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS
#define P2SB_SIZE (16 * MiB)
#endif