nb/intel/haswell/acpi: Align with Broadwell
Align cosmetics and move CTDP-specific ASL into its own file. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: I476a4e01016caa3658177b0fa8916576f4a5e0e5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46755 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
parent
4727663931
commit
c5381e0f36
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@ -0,0 +1,222 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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//Scope (\_SB.PCI0.MCHC)
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//{
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Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */
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Name (CTCC, 0) /* CTDP Current Selection */
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Name (CTCN, 0) /* CTDP Nominal Select */
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Name (CTCD, 1) /* CTDP Down Select */
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Name (CTCU, 2) /* CTDP Up Select */
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Name (SPL1, 0) /* Saved PL1 value */
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OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR + 0x5000, 0x1000)
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Field (MCHB, DWordAcc, Lock, Preserve)
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{
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Offset (0x930), /* PACKAGE_POWER_SKU */
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CTDN, 15, /* CTDP Nominal PL1 */
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Offset (0x938), /* PACKAGE_POWER_SKU_UNIT */
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PUNI, 4, /* Power Units */
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, 4,
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EUNI, 5, /* Energy Units */
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, 3,
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TUNI, 4, /* Time Units */
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Offset (0x958), /* PLATFORM_INFO */
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, 40,
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LFM_, 8, /* Maximum Efficiency Ratio (LFM) */
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Offset (0x9a0), /* TURBO_POWER_LIMIT1 */
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PL1V, 15, /* Power Limit 1 Value */
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PL1E, 1, /* Power Limit 1 Enable */
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PL1C, 1, /* Power Limit 1 Clamp */
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PL1T, 7, /* Power Limit 1 Time */
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Offset (0x9a4), /* TURBO_POWER_LIMIT2 */
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PL2V, 15, /* Power Limit 2 Value */
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PL2E, 1, /* Power Limit 2 Enable */
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PL2C, 1, /* Power Limit 2 Clamp */
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PL2T, 7, /* Power Limit 2 Time */
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Offset (0xf3c), /* CONFIG_TDP_NOMINAL */
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TARN, 8, /* CTDP Nominal Turbo Activation Ratio */
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Offset (0xf40), /* CONFIG_TDP_LEVEL1 */
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CTDD, 15, /* CTDP Down PL1 */
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, 1,
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TARD, 8, /* CTDP Down Turbo Activation Ratio */
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Offset (0xf48), /* MSR_CONFIG_TDP_LEVEL2 */
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CTDU, 15, /* CTDP Up PL1 */
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, 1,
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TARU, 8, /* CTDP Up Turbo Activation Ratio */
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Offset (0xf50), /* CONFIG_TDP_CONTROL */
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CTCS, 2, /* CTDP Select */
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Offset (0xf54), /* TURBO_ACTIVATION_RATIO */
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TARS, 8, /* Turbo Activation Ratio Select */
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}
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/*
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* Search CPU0 _PSS looking for control = arg0 and then
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* return previous P-state entry number for new _PPC
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*
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* Format of _PSS:
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* Name (_PSS, Package () {
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* Package (6) { freq, power, tlat, blat, control, status }
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* }
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*/
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External (\_SB.CP00._PSS)
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Method (PSSS, 1, NotSerialized)
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{
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Local0 = 1 /* Start at P1 */
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Local1 = SizeOf (\_SB.CP00._PSS)
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While (Local0 < Local1) {
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/* Store _PSS entry Control value to Local2 */
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Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8
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If (Local2 == Arg0) {
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Return (Local0 - 1)
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}
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Local0++
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}
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Return (0)
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}
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/* Calculate PL2 based on chip type */
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Method (CPL2, 1, NotSerialized)
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{
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If (\ISLP ()) {
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/* Haswell ULT PL2 = 25W */
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Return (25 * 8)
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} Else {
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/* Haswell Mobile PL2 = 1.25 * PL1 */
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Return ((Arg0 * 125) / 100)
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}
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}
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/* Set Config TDP Down */
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Method (STND, 0, Serialized)
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{
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If (Acquire (CTCM, 100)) {
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Return (0)
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}
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If (CTCD == CTCC) {
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Release (CTCM)
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Return (0)
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}
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Debug = "Set TDP Down"
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/* Set CTC */
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CTCS = CTCD
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/* Set TAR */
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TARS = TARD
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/* Set PPC limit and notify OS */
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PPCM = PSSS (TARD)
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PPCN ()
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/* Set PL2 */
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PL2V = CPL2 (CTDD)
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/* Set PL1 */
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PL1V = CTDD
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/* Store the new TDP Down setting */
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CTCC = CTCD
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Release (CTCM)
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Return (1)
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}
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/* Set Config TDP Nominal from Down */
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Method (STDN, 0, Serialized)
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{
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If (Acquire (CTCM, 100)) {
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Return (0)
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}
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If (CTCN == CTCC) {
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Release (CTCM)
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Return (0)
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}
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Debug = "Set TDP Nominal"
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/* Set PL1 */
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PL1V = CTDN
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/* Set PL2 */
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PL2V = CPL2 (CTDN)
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/* Set PPC limit and notify OS */
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PPCM = PSSS (TARN)
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PPCN ()
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/* Set TAR */
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TARS = TARN
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/* Set CTC */
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CTCS = CTCN
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/* Store the new TDP Nominal setting */
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CTCC = CTCN
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Release (CTCM)
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Return (1)
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}
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/* Calculate PL1 value based on requested TDP */
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Method (TDPP, 1, NotSerialized)
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{
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Return (((PUNI - 1) << 2) * Arg0)
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}
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/* Enable Controllable TDP to limit PL1 to requested value */
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Method (CTLE, 1, Serialized)
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{
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If (Acquire (CTCM, 100)) {
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Return (0)
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}
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Debug = "Enable PL1 Limit"
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/* Set _PPC to LFM */
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Local0 = PSSS (LFM_)
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PPCM = Local0 + 1
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\PPCN ()
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/* Set TAR to LFM-1 */
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TARS = LFM_ - 1
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/* Set PL1 to desired value */
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SPL1 = PL1V
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PL1V = TDPP (Arg0)
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/* Set PL1 CLAMP bit */
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PL1C = 1
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Release (CTCM)
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Return (1)
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}
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/* Disable Controllable TDP */
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Method (CTLD, 0, Serialized)
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{
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If (Acquire (CTCM, 100)) {
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Return (0)
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}
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Debug = "Disable PL1 Limit"
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/* Clear PL1 CLAMP bit */
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PL1C = 0
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/* Set PL1 to normal value */
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PL1V = SPL1
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/* Set TAR to 0 */
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TARS = 0
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/* Set _PPC to 0 */
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PPCM = 0
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\PPCN ()
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Release (CTCM)
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Return (1)
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}
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//}
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@ -8,21 +8,21 @@
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/* PCI Device Resource Consumption */
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Device (PDRC)
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{
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Name (_HID, EISAID("PNP0C02"))
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Name (_HID, EISAID ("PNP0C02"))
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Name (_UID, 1)
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Name (PDRS, ResourceTemplate() {
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Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000)
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Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000)
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Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
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Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
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Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
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Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
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Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
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Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
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Name (PDRS, ResourceTemplate () {
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Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000)
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Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000)
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Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000)
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Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000)
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Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
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Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
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Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
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Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
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#if CONFIG(CHROMEOS_RAMOOPS)
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Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
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Memory32Fixed (ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
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CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
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#endif
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})
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@ -30,6 +30,6 @@ Device (PDRC)
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// Current Resource Settings
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Method (_CRS, 0, Serialized)
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{
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Return(PDRS)
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Return (PDRS)
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}
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}
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@ -1,15 +1,15 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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Name(_HID,EISAID("PNP0A08")) // PCIe
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Name(_CID,EISAID("PNP0A03")) // PCI
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Name (_HID, EISAID ("PNP0A08")) // PCIe
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Name (_CID, EISAID ("PNP0A03")) // PCI
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Name(_BBN, 0)
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Name (_BBN, 0)
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Device (MCHC)
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{
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Name(_ADR, 0x00000000) // 0:0.0
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Name (_ADR, 0x00000000) // 0:0.0
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OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
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OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
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Field (MCHP, DWordAcc, NoLock, Preserve)
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{
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Offset (0x40), // EPBAR
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@ -81,223 +81,7 @@ Device (MCHC)
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TLUD, 32,
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}
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Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */
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Name (CTCC, 0) /* CTDP Current Selection */
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Name (CTCN, 0) /* CTDP Nominal Select */
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Name (CTCD, 1) /* CTDP Down Select */
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Name (CTCU, 2) /* CTDP Up Select */
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Name (SPL1, 0) /* Saved PL1 value */
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OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR + 0x5000, 0x1000)
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Field (MCHB, DWordAcc, Lock, Preserve)
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{
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Offset (0x930), /* PACKAGE_POWER_SKU */
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CTDN, 15, /* CTDP Nominal PL1 */
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Offset (0x938), /* PACKAGE_POWER_SKU_UNIT */
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PUNI, 4, /* Power Units */
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, 4,
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EUNI, 5, /* Energy Units */
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, 3,
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TUNI, 4, /* Time Units */
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Offset (0x958), /* PLATFORM_INFO */
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, 40,
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LFM_, 8, /* Maximum Efficiency Ratio (LFM) */
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Offset (0x9a0), /* TURBO_POWER_LIMIT1 */
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PL1V, 15, /* Power Limit 1 Value */
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PL1E, 1, /* Power Limit 1 Enable */
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PL1C, 1, /* Power Limit 1 Clamp */
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PL1T, 7, /* Power Limit 1 Time */
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Offset (0x9a4), /* TURBO_POWER_LIMIT2 */
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PL2V, 15, /* Power Limit 2 Value */
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PL2E, 1, /* Power Limit 2 Enable */
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PL2C, 1, /* Power Limit 2 Clamp */
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PL2T, 7, /* Power Limit 2 Time */
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Offset (0xf3c), /* CONFIG_TDP_NOMINAL */
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TARN, 8, /* CTDP Nominal Turbo Activation Ratio */
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Offset (0xf40), /* CONFIG_TDP_LEVEL1 */
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CTDD, 15, /* CTDP Down PL1 */
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, 1,
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TARD, 8, /* CTDP Down Turbo Activation Ratio */
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Offset (0xf48), /* MSR_CONFIG_TDP_LEVEL2 */
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CTDU, 15, /* CTDP Up PL1 */
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, 1,
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TARU, 8, /* CTDP Up Turbo Activation Ratio */
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Offset (0xf50), /* CONFIG_TDP_CONTROL */
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CTCS, 2, /* CTDP Select */
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Offset (0xf54), /* TURBO_ACTIVATION_RATIO */
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TARS, 8, /* Turbo Activation Ratio Select */
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}
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/*
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* Search CPU0 _PSS looking for control = arg0 and then
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* return previous P-state entry number for new _PPC
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*
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* Format of _PSS:
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* Name (_PSS, Package () {
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* Package (6) { freq, power, tlat, blat, control, status }
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* }
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*/
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External (\_SB.CP00._PSS)
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Method (PSSS, 1, NotSerialized)
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{
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Local0 = 1 /* Start at P1 */
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Local1 = SizeOf (\_SB.CP00._PSS)
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While (Local0 < Local1) {
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/* Store _PSS entry Control value to Local2 */
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Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8
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If (Local2 == Arg0) {
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Return (Local0 - 1)
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}
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Local0++
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}
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Return (0)
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}
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/* Calculate PL2 based on chip type */
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Method (CPL2, 1, NotSerialized)
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{
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If (\ISLP ()) {
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/* Haswell ULT PL2 = 25W */
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Return (25 * 8)
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} Else {
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/* Haswell Mobile PL2 = 1.25 * PL1 */
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Return ((Arg0 * 125) / 100)
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}
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}
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/* Set Config TDP Down */
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Method (STND, 0, Serialized)
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{
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If (Acquire (CTCM, 100)) {
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Return (0)
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}
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If (CTCD == CTCC) {
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Release (CTCM)
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Return (0)
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}
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Debug = "Set TDP Down"
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/* Set CTC */
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CTCS = CTCD
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/* Set TAR */
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TARS = TARD
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/* Set PPC limit and notify OS */
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PPCM = PSSS (TARD)
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PPCN ()
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/* Set PL2 */
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PL2V = CPL2 (CTDD)
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/* Set PL1 */
|
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PL1V = CTDD
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|
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/* Store the new TDP Down setting */
|
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CTCC = CTCD
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Release (CTCM)
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Return (1)
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}
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/* Set Config TDP Nominal from Down */
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Method (STDN, 0, Serialized)
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{
|
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If (Acquire (CTCM, 100)) {
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Return (0)
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}
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If (CTCN == CTCC) {
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Release (CTCM)
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Return (0)
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}
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Debug = "Set TDP Nominal"
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/* Set PL1 */
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PL1V = CTDN
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/* Set PL2 */
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PL2V = CPL2 (CTDN)
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|
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/* Set PPC limit and notify OS */
|
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PPCM = PSSS (TARN)
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PPCN ()
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/* Set TAR */
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TARS = TARN
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/* Set CTC */
|
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CTCS = CTCN
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|
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/* Store the new TDP Nominal setting */
|
||||
CTCC = CTCN
|
||||
|
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Release (CTCM)
|
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Return (1)
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}
|
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|
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/* Calculate PL1 value based on requested TDP */
|
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Method (TDPP, 1, NotSerialized)
|
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{
|
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Return (((PUNI - 1) << 2) * Arg0)
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}
|
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|
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/* Enable Controllable TDP to limit PL1 to requested value */
|
||||
Method (CTLE, 1, Serialized)
|
||||
{
|
||||
If (Acquire (CTCM, 100)) {
|
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Return (0)
|
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}
|
||||
|
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Debug = "Enable PL1 Limit"
|
||||
|
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/* Set _PPC to LFM */
|
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Local0 = PSSS (LFM_)
|
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PPCM = Local0 + 1
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\PPCN ()
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/* Set TAR to LFM-1 */
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TARS = LFM_ - 1
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|
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/* Set PL1 to desired value */
|
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SPL1 = PL1V
|
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PL1V = TDPP (Arg0)
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||||
|
||||
/* Set PL1 CLAMP bit */
|
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PL1C = 1
|
||||
|
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Release (CTCM)
|
||||
Return (1)
|
||||
}
|
||||
|
||||
/* Disable Controllable TDP */
|
||||
Method (CTLD, 0, Serialized)
|
||||
{
|
||||
If (Acquire (CTCM, 100)) {
|
||||
Return (0)
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||||
}
|
||||
|
||||
Debug = "Disable PL1 Limit"
|
||||
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/* Clear PL1 CLAMP bit */
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PL1C = 0
|
||||
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/* Set PL1 to normal value */
|
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PL1V = SPL1
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/* Set TAR to 0 */
|
||||
TARS = 0
|
||||
|
||||
/* Set _PPC to 0 */
|
||||
PPCM = 0
|
||||
\PPCN ()
|
||||
|
||||
Release (CTCM)
|
||||
Return (1)
|
||||
}
|
||||
#include "ctdp.asl"
|
||||
}
|
||||
|
||||
// Current Resource Settings
|
||||
|
|
@ -418,9 +202,9 @@ Name (MCRS, ResourceTemplate()
|
|||
Method (_CRS, 0, Serialized)
|
||||
{
|
||||
// Find PCI resource area in MCRS
|
||||
CreateDwordField(MCRS, ^PM01._MIN, PMIN)
|
||||
CreateDwordField(MCRS, ^PM01._MAX, PMAX)
|
||||
CreateDwordField(MCRS, ^PM01._LEN, PLEN)
|
||||
CreateDwordField (MCRS, ^PM01._MIN, PMIN)
|
||||
CreateDwordField (MCRS, ^PM01._MAX, PMAX)
|
||||
CreateDwordField (MCRS, ^PM01._LEN, PLEN)
|
||||
|
||||
// Fix up PCI memory region
|
||||
// Start with Top of Lower Usable DRAM
|
||||
|
|
@ -439,7 +223,7 @@ Method (_CRS, 0, Serialized)
|
|||
|
||||
PMIN = Local0
|
||||
PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1
|
||||
PLEN = PMAX - PMIN + 1
|
||||
PLEN = (PMAX - PMIN) + 1
|
||||
|
||||
Return (MCRS)
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue