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mb/google/volteer/var/voxel: Update DPTF parameters 

update the DPTF parameters received from the thermal team.

BUG=b:167523658
TEST=emerge-volteer coreboot

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Iafc3fb389ade5cfec79a816a28880262bdce7c74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47858
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sheng-Liang Pan 2020-11-23 16:06:44 +08:00 committed by Tim Wawrzynczak
parent 17a798b68c
commit c5395bc95d
1 changed files with 6 additions and 6 deletions
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12
src/mainboard/google/volteer/variants/voxel/overridetree.cb
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@ -23,22 +23,22 @@ chip soc/intel/tigerlake
## Active Policy ## Active Policy
register "policies.active" = "{ register "policies.active" = "{
[0] = {.target = DPTF_CPU, [0] = {.target = DPTF_CPU,
.thresholds = {TEMP_PCT(94, 100),}}, .thresholds = {TEMP_PCT(98, 100),}},
[1] = {.target = DPTF_TEMP_SENSOR_2, [1] = {.target = DPTF_TEMP_SENSOR_2,
.thresholds = {TEMP_PCT(64, 100), .thresholds = {TEMP_PCT(64, 100),
TEMP_PCT(60, 90), TEMP_PCT(60, 90),
TEMP_PCT(56, 80), TEMP_PCT(56, 80),
TEMP_PCT(52, 70), TEMP_PCT(52, 70),
TEMP_PCT(48, 60), TEMP_PCT(47, 60),
TEMP_PCT(44, 50), TEMP_PCT(42, 50),
TEMP_PCT(40, 40),}}}" TEMP_PCT(35, 40),}}}"
## Passive Policy ## Passive Policy
register "policies.passive" = "{ register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000),
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000),
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 54, 6000), [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 52, 6000),
[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}" [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}"
## Critical Policy ## Critical Policy
@ -58,7 +58,7 @@ chip soc/intel/tigerlake
.time_window_min = 28 * MSECS_PER_SEC, .time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,}, .granularity = 200,},
.pl2 = {.min_power = 15000, .pl2 = {.min_power = 51000,
.max_power = 51000, .max_power = 51000,
.time_window_min = 28 * MSECS_PER_SEC, .time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC,