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soc/mediatek/mt8186: Change the power-down time slot from 0xA to 0xF 

PMIC_CPSDSA4[4:0] controls the power-down at the specified time slot.
Setting it to 0xA would cause an extra delay of 20ms compared to 0xF.
The value of time slot is from 0x0 to 0x1F which represents the delay
when reset occurs.

To avoid the delay, change the value from 0xA to 0xF.

This modification is based on chapter 3.7 in the MT8186 functional
specification.

BUG=b:218630683, b:218630684
TEST=the power-off waveform is correct.

Signed-off-by: zhiyong tao <zhiyong.tao@mediatek.corp-partner.google.com>
Change-Id: I537fe87740f0f8c25b923d7d536e81503b71762b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64038
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
zhiyong tao 2022-05-04 10:46:12 +08:00 committed by Hung-Te Lin
parent 4c684877d1
commit c53a0aaa59
1 changed files with 2 additions and 2 deletions
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4
src/soc/mediatek/mt8186/mt6366.c
View File

@ -807,8 +807,8 @@ static void wk_sleep_voltage_by_ddr(void)
static void wk_power_down_seq(void)
{
mt6366_protect_control(false);
/* Set VPROC12 sequence to VA12 */
pwrap_write_field(PMIC_CPSDSA4, 0xA, 0x1F, 0);
/* Set VPROC12 power-down time slot to 0xF to avoid 20ms delay */
pwrap_write_field(PMIC_CPSDSA4, 0xF, 0x1F, 0);
mt6366_protect_control(true);
}