GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/hp/z220_series: Add configs for integrated XHCI 

Without these, all SuperSpeed ports are wired to EHCI #2.

"superspeed_capable_ports" and "xhci_switchable_ports" should fit both
CMT and SFF variants, while "xhci_overcurrent_mapping" should be
consistent with the first 4 elements of mainboard_usb_ports[].

With this commit, SuperSpeed devices plugged in SuperSpeed ports are
wired to the XHCI on my own Z220 SFF.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Ifddecfd1d32ed6ab84d7eed8dc2d85d83cbebbcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67089
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Bill XIE 2022-08-26 09:46:41 +08:00 committed by Felix Held
parent 8dfb0f9111
commit c547996c7c
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/hp/z220_series/devicetree.cb
View File

@ -33,6 +33,9 @@ chip northbridge/intel/sandybridge
register "sata_interface_speed_support" = "0x3" register "sata_interface_speed_support" = "0x3"
register "spi_lvscc" = "0x2005" register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005" register "spi_uvscc" = "0x2005"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_switchable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x0000000f"
device pci 14.0 on end # xHCI device pci 14.0 on end # xHCI
device pci 16.0 on end # Management Engine Interface 1 device pci 16.0 on end # Management Engine Interface 1