mb/google/guybrush: Enable RTD3 support for NVMe

This will tell the kernel to ignore PCI ASPM when suspending the device
and instead place the device into D3. We don't actually have a pin to
control power to the NVMe so we leave it in D3Hot. I'm not sure if
`PCI_RST#` is working correctly on S0i3 suspend/resume. If it's not
acting as expected we can add the reset GPIO and have the OS do it.

BUG=b:184617186
TEST=Run suspend_stress_test on guybrush for 10 cycles

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I29539ac120a9f1b7c1bfeaca745cfc82acfa461a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54967
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/guybrush/Kconfig

@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
+	select DRIVERS_PCIE_RTD3_DEVICE
 	select DRIVERS_UART_ACPI
 	select DRIVERS_WIFI_GENERIC
 	select EC_GOOGLE_CHROMEEC

src/mainboard/google/guybrush/variants/baseboard/devicetree.cb

@@ -193,7 +193,13 @@ chip soc/amd/cezanne
 		end # WLAN
 		device ref gpp_bridge_1 on end # SD
 		device ref gpp_bridge_2 on end # WWAN
-		device ref gpp_bridge_3 on end # NVMe
+		device ref gpp_bridge_3 on
+			# Required so the NVMe gets placed into D3 when entering S0i3.
+			chip drivers/pcie/rtd3/device
+				register "name" = ""NVME""
+				device pci 00.0 on end
+			end
+		end # NVMe
 
 		device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
 			device ref gfx on end # Internal GPU (GFX)