cpu/intel/haswell: Rework acpi/cpu.asl
Use acpigen_write_processor_cnot to implement notifications the CPU. Generate PPKG in SSDT. Change-Id: I126989e8737720f55f7ce113ff4e32bfe0f22620 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29885 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -339,6 +339,13 @@ void generate_cpu_entries(struct device *device)
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acpigen_pop_len();
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acpigen_pop_len();
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}
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}
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}
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}
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/* PPKG is usually used for thermal management
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of the first and only package. */
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acpigen_write_processor_package("PPKG", 0, cores_per_package);
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/* Add a method to notify processor nodes */
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acpigen_write_processor_cnot(cores_per_package);
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}
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}
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struct chip_operations cpu_intel_haswell_ops = {
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struct chip_operations cpu_intel_haswell_ops = {
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@ -14,84 +14,23 @@
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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*/
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*/
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/* These devices are created at runtime */
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/* These come from the dynamically created CPU SSDT */
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External (\_PR.CP00, DeviceObj)
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External (\_PR.CNOT, MethodObj)
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External (\_PR.CP01, DeviceObj)
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External (\_PR.CP02, DeviceObj)
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External (\_PR.CP03, DeviceObj)
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External (\_PR.CP04, DeviceObj)
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External (\_PR.CP05, DeviceObj)
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External (\_PR.CP06, DeviceObj)
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External (\_PR.CP07, DeviceObj)
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/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
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/* Notify OS to re-read CPU tables */
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Method (PNOT)
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Method (PNOT)
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{
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{
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If (LGreaterEqual (\PCNT, 2)) {
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\_PR.CNOT (0x81)
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Notify (\_PR.CP00, 0x81) // _CST
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Notify (\_PR.CP01, 0x81) // _CST
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}
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If (LGreaterEqual (\PCNT, 4)) {
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Notify (\_PR.CP02, 0x81) // _CST
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Notify (\_PR.CP03, 0x81) // _CST
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}
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If (LGreaterEqual (\PCNT, 8)) {
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Notify (\_PR.CP04, 0x81) // _CST
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Notify (\_PR.CP05, 0x81) // _CST
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Notify (\_PR.CP06, 0x81) // _CST
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Notify (\_PR.CP07, 0x81) // _CST
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}
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}
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}
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/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */
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/* Notify OS to re-read CPU _PPC limit */
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Method (PPCN)
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Method (PPCN)
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{
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{
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If (LGreaterEqual (\PCNT, 2)) {
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\_PR.CNOT (0x80)
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Notify (\_PR.CP00, 0x80) // _PPC
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Notify (\_PR.CP01, 0x80) // _PPC
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}
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If (LGreaterEqual (\PCNT, 4)) {
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Notify (\_PR.CP02, 0x80) // _PPC
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Notify (\_PR.CP03, 0x80) // _PPC
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}
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If (LGreaterEqual (\PCNT, 8)) {
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Notify (\_PR.CP04, 0x80) // _PPC
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Notify (\_PR.CP05, 0x80) // _PPC
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Notify (\_PR.CP06, 0x80) // _PPC
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Notify (\_PR.CP07, 0x80) // _PPC
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}
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}
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}
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/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */
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/* Notify OS to re-read Throttle Limit tables */
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Method (TNOT)
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Method (TNOT)
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{
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{
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If (LGreaterEqual (\PCNT, 2)) {
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\_PR.CNOT (0x82)
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Notify (\_PR.CP00, 0x82) // _TPC
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Notify (\_PR.CP01, 0x82) // _TPC
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}
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If (LGreaterEqual (\PCNT, 4)) {
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Notify (\_PR.CP02, 0x82) // _TPC
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Notify (\_PR.CP03, 0x82) // _TPC
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}
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If (LGreaterEqual (\PCNT, 8)) {
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Notify (\_PR.CP04, 0x82) // _TPC
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Notify (\_PR.CP05, 0x82) // _TPC
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Notify (\_PR.CP06, 0x82) // _TPC
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Notify (\_PR.CP07, 0x82) // _TPC
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}
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}
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/* Return a package containing enabled processor entries */
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Method (PPKG)
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{
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If (LGreaterEqual (\PCNT, 8)) {
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Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03,
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\_PR.CP04, \_PR.CP05, \_PR.CP06, \_PR.CP07})
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} ElseIf (LGreaterEqual (\PCNT, 4)) {
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Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03})
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} ElseIf (LGreaterEqual (\PCNT, 2)) {
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Return (Package() {\_PR.CP00, \_PR.CP01})
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} Else {
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Return (Package() {\_PR.CP00})
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}
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}
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}
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@ -13,6 +13,8 @@
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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*/
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*/
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External (\PPKG, MethodObj)
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#include <variant/thermal.h>
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#include <variant/thermal.h>
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// Thermal Zone
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// Thermal Zone
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@ -15,6 +15,8 @@
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// Thermal Zone
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// Thermal Zone
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External (\PPKG, MethodObj)
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#define HAVE_THERMALZONE
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#define HAVE_THERMALZONE
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Scope (\_TZ)
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Scope (\_TZ)
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{
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{
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@ -15,6 +15,8 @@
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// Thermal Zone
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// Thermal Zone
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External (\PPKG, MethodObj)
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Scope (\_TZ)
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Scope (\_TZ)
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{
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{
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ThermalZone (THRM)
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ThermalZone (THRM)
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