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soc/skylake: prevent null pointer dereferences 

Change-Id: Ide10223e7fc37a6c4bfa408234ef3efe1846236a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Angel Pons 2019-08-30 22:14:18 +02:00 committed by Patrick Georgi
parent 3647920722
commit c54dcf499b
2 changed files with 19 additions and 20 deletions
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16
src/soc/intel/skylake/chip.c
View File

@ -153,10 +153,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
/* Enable ISH if device is on */ /* Enable ISH if device is on */
dev = pcidev_path_on_root(PCH_DEVFN_ISH); dev = pcidev_path_on_root(PCH_DEVFN_ISH);
if (dev) params->IshEnable = dev ? dev->enabled : 0;
params->IshEnable = dev->enabled;
else
params->IshEnable = 0;
params->EnableAzalia = config->EnableAzalia; params->EnableAzalia = config->EnableAzalia;
params->IoBufferOwnership = config->IoBufferOwnership; params->IoBufferOwnership = config->IoBufferOwnership;
@ -210,23 +207,24 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
* do the changes and then lock it back in coreboot * do the changes and then lock it back in coreboot
* *
*/ */
if (config->HeciEnabled == 0) params->PsfUnlock = !config->HeciEnabled;
params->PsfUnlock = 1;
else
params->PsfUnlock = 0;
for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
fill_vr_domain_config(params, i, &config->domain_vr_config[i]); fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
/* Show SPI controller if enabled in devicetree.cb */ /* Show SPI controller if enabled in devicetree.cb */
dev = pcidev_path_on_root(PCH_DEVFN_SPI); dev = pcidev_path_on_root(PCH_DEVFN_SPI);
params->ShowSpiController = dev->enabled; params->ShowSpiController = dev ? dev->enabled : 0;
/* Enable xDCI controller if enabled in devicetree and allowed */ /* Enable xDCI controller if enabled in devicetree and allowed */
dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
if (dev) {
if (!xdci_can_enable()) if (!xdci_can_enable())
dev->enabled = 0; dev->enabled = 0;
params->XdciEnable = dev->enabled; params->XdciEnable = dev->enabled;
} else {
params->XdciEnable = 0;
}
params->SendVrMbxCmd = config->SendVrMbxCmd; params->SendVrMbxCmd = config->SendVrMbxCmd;

11
src/soc/intel/skylake/chip_fsp20.c
View File

@ -354,10 +354,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* If ISH is enabled, enable ISH elements */ /* If ISH is enabled, enable ISH elements */
dev = pcidev_path_on_root(PCH_DEVFN_ISH); dev = pcidev_path_on_root(PCH_DEVFN_ISH);
if (dev) params->PchIshEnable = dev ? dev->enabled : 0;
params->PchIshEnable = dev->enabled;
else
params->PchIshEnable = 0;
params->PchHdaEnable = config->EnableAzalia; params->PchHdaEnable = config->EnableAzalia;
params->PchHdaIoBufferOwnership = config->IoBufferOwnership; params->PchHdaIoBufferOwnership = config->IoBufferOwnership;
@ -433,13 +430,17 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Show SPI controller if enabled in devicetree.cb */ /* Show SPI controller if enabled in devicetree.cb */
dev = pcidev_path_on_root(PCH_DEVFN_SPI); dev = pcidev_path_on_root(PCH_DEVFN_SPI);
params->ShowSpiController = dev->enabled; params->ShowSpiController = dev ? dev->enabled : 0;
/* Enable xDCI controller if enabled in devicetree and allowed */ /* Enable xDCI controller if enabled in devicetree and allowed */
dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
if (dev) {
if (!xdci_can_enable()) if (!xdci_can_enable())
dev->enabled = 0; dev->enabled = 0;
params->XdciEnable = dev->enabled; params->XdciEnable = dev->enabled;
} else {
params->XdciEnable = 0;
}
/* Enable or disable Gaussian Mixture Model in devicetree */ /* Enable or disable Gaussian Mixture Model in devicetree */
dev = pcidev_path_on_root(SA_DEVFN_GMM); dev = pcidev_path_on_root(SA_DEVFN_GMM);