diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index ec07c18506..7b6b401273 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -761,17 +761,12 @@ static void domain_enable_resources(device_t dev)
 	u32 val;
 
 #if CONFIG_AMD_SB_CIMX
-  #if CONFIG_HAVE_ACPI_RESUME
-	if (acpi_slp_type != 3) {
+	if (!acpi_is_wakeup_s3()) {
 		sb_After_Pci_Init();
 		sb_Mid_Post_Init();
 	} else {
 		sb_After_Pci_Restore_Init();
 	}
-  #else
-	sb_After_Pci_Init();
-	sb_Mid_Post_Init();
-  #endif
 #endif
 
 	/* Must be called after PCI enumeration and resource allocation */
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index f4c5fd44e2..8000601930 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -498,14 +498,10 @@ static void sb800_enable(device_t dev)
 		/* call the CIMX entry at the last sb800 device,
 		 * so make sure the mainboard devicetree is complete
 		 */
-#if CONFIG_HAVE_ACPI_RESUME
-		if (acpi_slp_type != 3)
+		if (!acpi_is_wakeup_s3())
 			sb_Before_Pci_Init();
 		else
 			sb_Before_Pci_Restore_Init();
-#else
-		sb_Before_Pci_Init();
-#endif
 		break;
 
 	default: