soc/mediatek/mt8183: Correct continuation line indent
BRANCH=kukui BUG=none TEST=emerge-kukui coreboot Change-Id: I9d01d24d3494f2eb28cfb411e13adf3b6717d191 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36285 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -88,12 +88,12 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term,
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imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >>
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24) & 0x1;
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dramc_dbg("1. OCD DRVP=%d CALOUT=%d\n",
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impx_drv, imp_cal_result);
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impx_drv, imp_cal_result);
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if (imp_cal_result == 1 && DRVP_result == 0xff) {
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DRVP_result = impx_drv;
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dramc_dbg("1. OCD DRVP calibration OK! DRVP=%d\n",
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DRVP_result);
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DRVP_result);
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break;
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}
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}
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@ -116,12 +116,12 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term,
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imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >>
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24) & 0x1;
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dramc_dbg("3. OCD ODTN=%d CALOUT=%d\n",
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impx_drv, imp_cal_result);
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impx_drv, imp_cal_result);
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if (imp_cal_result == 0 && ODTN_result == 0xff) {
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ODTN_result = impx_drv;
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dramc_dbg("3. OCD ODTN calibration OK! ODTN=%d\n",
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ODTN_result);
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ODTN_result);
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break;
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}
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}
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