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soc/skylake/vr_config: fix VR config for KBL-U CPUs 

These changes are in accordance with the documentation:
[1] page 106, 7th Generation Intel(R) Processor Families for U/Y
    Platforms and 8th Generation Intel(R) Processor Family for U Quad
    Core and Y Dual Core Platforms. Datasheet, Volume 1. January 2019.
    Document Number: 334661-006

Change-Id: I5232a7a670b97d51ff3b3b71a08f25f961ac1d6f
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36058
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maxim Polyakov 2019-10-15 14:13:28 +03:00 committed by Patrick Georgi
parent 29f12e4d48
commit c56ca6ba17
1 changed files with 15 additions and 6 deletions
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21
src/soc/intel/skylake/vr_config.c
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@ -121,15 +121,17 @@ static uint16_t get_sku_icc_max(int domain)
* SKL-U + OPC (15W) GT3 dual 5.1 29 57/19 * SKL-U + OPC (15W) GT3 dual 5.1 29 57/19
* SKL-U (15W) GT2 dual 4.5 29 31 * SKL-U (15W) GT2 dual 4.5 29 31
* *
* KBL-U/R + OPC (28W) GT3 dual 5.1 32 57/19 * KBL-U + OPC (28W) GT3 dual 5.1 32 57/19
* KBL-U/R + OPC (15W) GT3 dual 5.1 32 57/19 * KBL-U + OPC (15W) GT3 dual 5.1 32 57/19
* KBL-U (15W) GT1/2 dual 4.5 32 31
* KBL-U [*] (15W) GT1 quad 4.5 29 31
* *
* KBL-U/R (15W) GT2 quad 6 64 31 * KBL-U/R (15W) GT2 quad 6 64 31
* KBL-U/R (15W) GT1/2 dual 4.5 32 31
* KBL-U/R (15W) GT2 quad 4.5 29 31
* *
* SKL/KBL-Y (6W) 4.1 24 24 * SKL/KBL-Y (6W) 4.1 24 24
* SKL/KBL-Y (4.5W) 4.1 24 24 * SKL/KBL-Y (4.5W) 4.1 24 24
*
* [*] Pentium/Celeron CPUs with HD Graphics 610
*/ */
switch (mch_id) { switch (mch_id) {
@ -220,10 +222,17 @@ static uint16_t get_sku_icc_max(int domain)
case PCI_DEVICE_ID_INTEL_KBL_ID_U: { case PCI_DEVICE_ID_INTEL_KBL_ID_U: {
uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(4.5, 32, 31, 31); uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(4.5, 32, 31, 31);
if ((igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1) || if (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM)
(igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2))
icc_max[VR_IA_CORE] = VR_CFG_AMP(29); icc_max[VR_IA_CORE] = VR_CFG_AMP(29);
else if ((igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1) ||
(igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2)) {
const uint16_t icc_max_gt3[NUM_VR_DOMAINS] =
VR_CFG_ALL_DOMAINS_ICC(5.1, 32, 57, 19);
return icc_max_gt3[domain];
}
return icc_max[domain]; return icc_max[domain];
} }
default: default: