From c57494722319274710533b99692e29510b5cf5ba Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Sun, 24 Nov 2019 16:32:05 +0100
Subject: [PATCH] AGESA,binaryPI: Remove redundant SSE enable
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Change-Id: Ib3bf731b74cb20e886d3ecd483b37b1e3fc64ebf
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37349
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/amd/agesa/cache_as_ram.S | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S
index e3e5735c3b..e429bba966 100644
--- a/src/drivers/amd/agesa/cache_as_ram.S
+++ b/src/drivers/amd/agesa/cache_as_ram.S
@@ -22,7 +22,6 @@
  */
 
 #include "gcccar.inc"
-#include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
 
 .code32
@@ -35,15 +34,6 @@ _cache_as_ram_setup:
 
 	post_code(0xa0)
 
-	/* enable SSE2 128bit instructions */
-	/* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
-
-	movl	%cr4, %eax
-	orl	$(3 << 9), %eax
-	movl	%eax, %cr4
-
-	post_code(0xa1)
-
 	AMD_ENABLE_STACK
 
 	/* Align the stack. */