nb/intel/i945: Initialize console in bootblock

Change-Id: Ic6ea158714998195614a63ee46a057f405de5616
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This commit is contained in:
Arthur Heymans 2019-11-12 23:48:42 +01:00 committed by Patrick Georgi
parent e27c013f39
commit c583920a74
25 changed files with 44 additions and 21 deletions

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@ -1,5 +1,6 @@
ifeq ($(CONFIG_EC_LENOVO_PMH7),y) ifeq ($(CONFIG_EC_LENOVO_PMH7),y)
bootblock-y += pmh7.c
ramstage-y += pmh7.c ramstage-y += pmh7.c
smm-y += pmh7.c smm-y += pmh7.c
romstage-y += pmh7.c romstage-y += pmh7.c

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@ -1 +1,3 @@
romstage-y += gpio.c romstage-y += gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -1,2 +1,4 @@
ramstage-y += cstates.c ramstage-y += cstates.c
romstage-y += gpio.c romstage-y += gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -15,6 +15,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <bootblock_common.h>
#include <stdint.h> #include <stdint.h>
#include <cf9_reset.h> #include <cf9_reset.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
@ -111,7 +112,7 @@ void mainboard_pre_raminit_config(int s3_resume)
} }
} }
void mainboard_superio_config(void) void bootblock_mainboard_early_init(void)
{ {
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
} }

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@ -15,3 +15,5 @@
ramstage-y += cstates.c ramstage-y += cstates.c
romstage-y += gpio.c romstage-y += gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -14,6 +14,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <bootblock_common.h>
#include <stdint.h> #include <stdint.h>
#include <arch/io.h> #include <arch/io.h>
#include <delay.h> #include <delay.h>
@ -75,7 +76,7 @@ static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
outb(0xaa, port); outb(0xaa, port);
} }
void mainboard_superio_config(void) void bootblock_mainboard_early_init(void)
{ {
pnp_devfn_t dev; pnp_devfn_t dev;

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@ -1,2 +1,4 @@
ramstage-y += cstates.c ramstage-y += cstates.c
romstage-y += gpio.c romstage-y += gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -14,6 +14,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <bootblock_common.h>
#include <superio/ite/it8718f/it8718f.h> #include <superio/ite/it8718f/it8718f.h>
#include <superio/ite/common/ite.h> #include <superio/ite/common/ite.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
@ -24,7 +25,7 @@
#define EC_DEV PNP_DEV(0x2e, IT8718F_EC) #define EC_DEV PNP_DEV(0x2e, IT8718F_EC)
#define SUPERIO_DEV PNP_DEV(0x2e, 0) #define SUPERIO_DEV PNP_DEV(0x2e, 0)
void mainboard_superio_config(void) void bootblock_mainboard_early_init(void)
{ {
/* Set default GPIOs on superio */ /* Set default GPIOs on superio */
ite_reg_write(GPIO_DEV, 0x25, 0x40); ite_reg_write(GPIO_DEV, 0x25, 0x40);

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@ -1,3 +1,5 @@
ramstage-y += superio_hwm.c ramstage-y += superio_hwm.c
ramstage-y += cstates.c ramstage-y += cstates.c
romstage-y += gpio.c romstage-y += gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -13,6 +13,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <bootblock_common.h>
#include <stdint.h> #include <stdint.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
@ -29,7 +30,7 @@
* Also set up the GPIOs from the beginning. This is the "no schematic * Also set up the GPIOs from the beginning. This is the "no schematic
* but safe anyways" method. * but safe anyways" method.
*/ */
void mainboard_superio_config(void) void bootblock_mainboard_early_init(void)
{ {
pnp_devfn_t dev; pnp_devfn_t dev;

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@ -1,2 +1,4 @@
ramstage-y += cstates.c ramstage-y += cstates.c
romstage-y += gpio.c romstage-y += gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -13,6 +13,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <bootblock_common.h>
#include <superio/smsc/lpc47m15x/lpc47m15x.h> #include <superio/smsc/lpc47m15x/lpc47m15x.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/i82801gx/i82801gx.h>
@ -39,7 +40,7 @@ void mainboard_late_rcba_config(void)
// RCBA32(0x341c) = 0x00000001; // RCBA32(0x341c) = 0x00000001;
} }
void mainboard_superio_config(void) void bootblock_mainboard_early_init(void)
{ {
/* Enable SuperIO PM */ /* Enable SuperIO PM */
lpc47m15x_enable_serial(PME_DEV, 0x680); lpc47m15x_enable_serial(PME_DEV, 0x680);

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@ -1,2 +1,4 @@
ramstage-y += cstates.c ramstage-y += cstates.c
romstage-y += gpio.c romstage-y += gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -13,6 +13,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <bootblock_common.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
@ -41,7 +42,7 @@ void mainboard_lpc_decode(void)
* the two. Also set up the GPIOs from the beginning. This is the "no schematic * the two. Also set up the GPIOs from the beginning. This is the "no schematic
* but safe anyways" method. * but safe anyways" method.
*/ */
void mainboard_superio_config(void) void bootblock_mainboard_early_init(void)
{ {
pnp_devfn_t dev; pnp_devfn_t dev;

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@ -14,5 +14,9 @@
## ##
smm-y += dock.c smm-y += dock.c
bootblock-y += dock.c
romstage-y += dock.c romstage-y += dock.c
bootblock-y += gpio.c
romstage-y += gpio.c romstage-y += gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -15,6 +15,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <bootblock_common.h>
#include <delay.h> #include <delay.h>
#include <stdint.h> #include <stdint.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
@ -48,7 +49,7 @@ static void early_superio_config(void)
pnp_set_enable(dev, 1); pnp_set_enable(dev, 1);
} }
void mainboard_superio_config(void) void bootblock_mainboard_early_init(void)
{ {
/* Set up GPIO's early since it is needed for dock init */ /* Set up GPIO's early since it is needed for dock init */
i82801gx_setup_bars(); i82801gx_setup_bars();

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@ -14,6 +14,10 @@
## ##
smm-y += dock.c smm-y += dock.c
bootblock-y += dock.c
romstage-y += dock.c romstage-y += dock.c
ramstage-y += dock.c ramstage-y += dock.c
bootblock-y += gpio.c
romstage-y += gpio.c romstage-y += gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -15,6 +15,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <bootblock_common.h>
#include <delay.h> #include <delay.h>
#include <stdint.h> #include <stdint.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
@ -48,7 +49,7 @@ static void early_superio_config(void)
pnp_set_enable(dev, 1); pnp_set_enable(dev, 1);
} }
void mainboard_superio_config(void) void bootblock_mainboard_early_init(void)
{ {
/* Set up GPIO's early since it is needed for dock init */ /* Set up GPIO's early since it is needed for dock init */
i82801gx_setup_bars(); i82801gx_setup_bars();

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@ -16,3 +16,5 @@
ramstage-y += m3885.c ramstage-y += m3885.c
ramstage-y += cstates.c ramstage-y += cstates.c
romstage-y += gpio.c romstage-y += gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c

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@ -14,6 +14,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <bootblock_common.h>
#include <stdint.h> #include <stdint.h>
#include <arch/io.h> #include <arch/io.h>
#include <cf9_reset.h> #include <cf9_reset.h>
@ -54,7 +55,7 @@ static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
outb(0xaa, port); outb(0xaa, port);
} }
void mainboard_superio_config(void) void bootblock_mainboard_early_init(void)
{ {
pnp_devfn_t dev; pnp_devfn_t dev;

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@ -28,7 +28,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select PARALLEL_MP select PARALLEL_MP
select C_ENVIRONMENT_BOOTBLOCK select C_ENVIRONMENT_BOOTBLOCK
select NO_BOOTBLOCK_CONSOLE
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
def_bool n def_bool n

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@ -378,8 +378,6 @@ u32 decode_tseg_size(const u8 esmramc);
/* Romstage mainboard callbacks */ /* Romstage mainboard callbacks */
/* Optional: Override the default LPC config. */ /* Optional: Override the default LPC config. */
void mainboard_lpc_decode(void); void mainboard_lpc_decode(void);
/* Optional: Initialize the superio for serial output. */
void mainboard_superio_config(void);
/* Optional: mainboard specific init after console init and before raminit. */ /* Optional: mainboard specific init after console init and before raminit. */
void mainboard_pre_raminit_config(int s3_resume); void mainboard_pre_raminit_config(int s3_resume);
/* Mainboard specific RCBA init. Happens after raminit. */ /* Mainboard specific RCBA init. Happens after raminit. */

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@ -28,10 +28,6 @@ __weak void mainboard_lpc_decode(void)
{ {
} }
__weak void mainboard_superio_config(void)
{
}
__weak void mainboard_pre_raminit_config(int s3_resume) __weak void mainboard_pre_raminit_config(int s3_resume)
{ {
} }
@ -51,12 +47,7 @@ void mainboard_romstage_entry(void)
enable_lapic(); enable_lapic();
i82801gx_lpc_setup();
mainboard_lpc_decode(); mainboard_lpc_decode();
mainboard_superio_config();
/* Set up the console */
console_init();
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE) {
system_reset(); system_reset();

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@ -32,6 +32,7 @@ bootblock-$(CONFIG_USBDEBUG) += usb_debug.c
romstage-$(CONFIG_USBDEBUG) += usb_debug.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c
ramstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c