From c58e3bd90a96bf01859d1c0af83926b1e17edff5 Mon Sep 17 00:00:00 2001
From: Keith Short <keithshort@chromium.org>
Date: Fri, 10 May 2019 11:14:31 -0600
Subject: [PATCH] post_code: add post code for video initialization failure

Add a new post code POST_VIDEO_FAILURE used when the Intel FSP silicon
initialization returns an error when graphics was also initialized.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: Ibc7f7defbed34038f445949010a37c8e368aae20
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
---
 Documentation/POSTCODES                 |  1 +
 src/drivers/intel/fsp2_0/silicon_init.c | 14 +++++++++++++-
 src/include/console/post_codes.h        |  7 +++++++
 3 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES
index a9d392a9b0..0e67dd173c 100644
--- a/Documentation/POSTCODES
+++ b/Documentation/POSTCODES
@@ -21,6 +21,7 @@ This is an (incomplete) list of POST codes emitted by coreboot v4.
 0xe2 Vendor binary (e.g. FSP) generated a fatal error
 0xe3 RAM could not be initialized
 0xe4 Critical hardware component could not initialize
+0xe5 Video subsystem failed to initialize
 0xf8 Entry into elf boot
 0xf3 Jumping to payload
 
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index b0a697d8cb..e9c29db40e 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -18,6 +18,7 @@
 #include <fsp/api.h>
 #include <fsp/util.h>
 #include <program_loading.h>
+#include <soc/intel/common/vbt.h>
 #include <stage_cache.h>
 #include <string.h>
 #include <timestamp.h>
@@ -29,6 +30,7 @@ static void do_silicon_init(struct fsp_header *hdr)
 	FSPS_UPD *upd, *supd;
 	fsp_silicon_init_fn silicon_init;
 	uint32_t status;
+	uint8_t postcode;
 
 	supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base);
 
@@ -59,8 +61,18 @@ static void do_silicon_init(struct fsp_header *hdr)
 	/* Handle any errors returned by FspSiliconInit */
 	fsp_handle_reset(status);
 	if (status != FSP_SUCCESS) {
+		if (vbt_get()) {
+			/* Attempted to initialize graphics. Assume failure
+			 * is related to a video failure.
+			 */
+			postcode = POST_VIDEO_FAILURE;
+		} else {
+			/* Other silicon initialization failed */
+			postcode = POST_HW_INIT_FAILURE;
+		}
 		printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status);
-		die("FspSiliconINit returned an error!\n");
+		die_with_post_code(postcode,
+			"FspSiliconINit returned an error!\n");
 	}
 }
 
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index ae277d82e2..c1917adaff 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -355,6 +355,13 @@
  */
 #define POST_HW_INIT_FAILURE			0xe4
 
+/**
+ * \brief Video failure
+ *
+ * Video subsystem failed to initialize.
+ */
+#define POST_VIDEO_FAILURE			0xe5
+
 /**
  * \brief TPM failure
  *