Indent model_fxx_init and model_10xx_init.
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson
parent
ae60855f91
commit
c58f1d1df6
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@ -43,26 +43,24 @@ extern device_t get_node_pci(u32 nodeid, u32 fn);
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msr_t rdmsr_amd(u32 index)
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{
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msr_t result;
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__asm__ __volatile__ (
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"rdmsr"
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: "=a" (result.lo), "=d" (result.hi)
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: "c" (index), "D" (0x9c5a203a)
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);
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return result;
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msr_t result;
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__asm__ __volatile__(
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"rdmsr"
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:"=a"(result.lo), "=d"(result.hi)
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:"c"(index), "D"(0x9c5a203a)
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);
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return result;
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}
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void wrmsr_amd(u32 index, msr_t msr)
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{
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__asm__ __volatile__ (
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__asm__ __volatile__(
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"wrmsr"
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: /* No outputs */
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: "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (0x9c5a203a)
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);
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: /* No outputs */
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:"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
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);
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}
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static void model_10xxx_init(device_t dev)
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{
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u8 i;
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@ -72,7 +70,7 @@ static void model_10xxx_init(device_t dev)
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u32 siblings;
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#endif
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id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
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id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
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printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
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/* Turn on caching if we haven't already */
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@ -85,11 +83,10 @@ static void model_10xxx_init(device_t dev)
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/* zero the machine check error status registers */
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msr.lo = 0;
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msr.hi = 0;
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for(i=0; i < 5; i++) {
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wrmsr(MCI_STATUS + (i * 4),msr);
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for (i = 0; i < 5; i++) {
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wrmsr(MCI_STATUS + (i * 4), msr);
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}
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enable_cache();
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/* Enable the local cpu apics */
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@ -107,7 +104,7 @@ static void model_10xxx_init(device_t dev)
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wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
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msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
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msr.hi |= 1 << (33-32);
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msr.hi |= 1 << (33 - 32);
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wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
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}
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printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
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@ -115,7 +112,7 @@ static void model_10xxx_init(device_t dev)
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/* DisableCf8ExtCfg */
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msr = rdmsr(NB_CFG_MSR);
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msr.hi &= ~(1 << (46-32));
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msr.hi &= ~(1 << (46 - 32));
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wrmsr(NB_CFG_MSR, msr);
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/* Write protect SMM space with SMMLOCK. */
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@ -128,6 +125,7 @@ static void model_10xxx_init(device_t dev)
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static struct device_operations cpu_dev_ops = {
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.init = model_10xxx_init,
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};
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static struct cpu_device_id cpu_table[] = {
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//AMD_GH_SUPPORT
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{ X86_VENDOR_AMD, 0x100f00 }, /* SH-F0 L1 */
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@ -144,7 +142,8 @@ static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */
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{ 0, 0 },
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};
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static const struct cpu_driver model_10xxx __cpu_driver = {
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.ops = &cpu_dev_ops,
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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@ -44,66 +44,66 @@ void cpus_ready_for_init(void)
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#if CONFIG_K8_REV_F_SUPPORT == 0
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int is_e0_later_in_bsp(int nodeid)
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{
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uint32_t val;
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uint32_t val_old;
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int e0_later;
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if(nodeid==0) { // we don't need to do that for node 0 in core0/node0
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return !is_cpu_pre_e0();
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}
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// d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
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device_t dev;
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dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid,2));
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if(!dev) return 0;
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val_old = pci_read_config32(dev, 0x80);
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val = val_old;
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val |= (1<<3);
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pci_write_config32(dev, 0x80, val);
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val = pci_read_config32(dev, 0x80);
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e0_later = !!(val & (1<<3));
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if(e0_later) { // pre_e0 bit 3 always be 0 and can not be changed
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pci_write_config32(dev, 0x80, val_old); // restore it
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}
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uint32_t val;
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uint32_t val_old;
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int e0_later;
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if (nodeid == 0) { // we don't need to do that for node 0 in core0/node0
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return !is_cpu_pre_e0();
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}
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// d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
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device_t dev;
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dev = dev_find_slot(0, PCI_DEVFN(0x18 + nodeid, 2));
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if (!dev)
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return 0;
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val_old = pci_read_config32(dev, 0x80);
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val = val_old;
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val |= (1 << 3);
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pci_write_config32(dev, 0x80, val);
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val = pci_read_config32(dev, 0x80);
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e0_later = !!(val & (1 << 3));
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if (e0_later) { // pre_e0 bit 3 always be 0 and can not be changed
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pci_write_config32(dev, 0x80, val_old); // restore it
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}
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return e0_later;
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return e0_later;
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}
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#endif
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#if CONFIG_K8_REV_F_SUPPORT == 1
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int is_cpu_f0_in_bsp(int nodeid)
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{
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uint32_t dword;
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device_t dev;
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dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 3));
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dword = pci_read_config32(dev, 0xfc);
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return (dword & 0xfff00) == 0x40f00;
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uint32_t dword;
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device_t dev;
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dev = dev_find_slot(0, PCI_DEVFN(0x18 + nodeid, 3));
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dword = pci_read_config32(dev, 0xfc);
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return (dword & 0xfff00) == 0x40f00;
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}
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#endif
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#define MCI_STATUS 0x401
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static inline msr_t rdmsr_amd(unsigned index)
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static inline msr_t rdmsr_amd(u32 index)
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{
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msr_t result;
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__asm__ __volatile__ (
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"rdmsr"
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: "=a" (result.lo), "=d" (result.hi)
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: "c" (index), "D" (0x9c5a203a)
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);
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return result;
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msr_t result;
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__asm__ __volatile__(
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"rdmsr"
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:"=a"(result.lo), "=d"(result.hi)
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:"c"(index), "D"(0x9c5a203a)
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);
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return result;
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}
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static inline void wrmsr_amd(unsigned index, msr_t msr)
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static inline void wrmsr_amd(u32 index, msr_t msr)
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{
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__asm__ __volatile__ (
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"wrmsr"
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: /* No outputs */
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: "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (0x9c5a203a)
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);
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__asm__ __volatile__(
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"wrmsr"
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: /* No outputs */
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:"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
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);
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}
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#define MTRR_COUNT 8
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#define ZERO_CHUNK_KB 0x800UL /* 2M */
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#define ZERO_CHUNK_KB 0x800UL /* 2M */
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#define TOLM_KB 0x400000UL
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struct mtrr {
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@ -119,11 +119,11 @@ struct mtrr_state {
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static void save_mtrr_state(struct mtrr_state *state)
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{
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int i;
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for(i = 0; i < MTRR_COUNT; i++) {
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for (i = 0; i < MTRR_COUNT; i++) {
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state->mtrrs[i].base = rdmsr(MTRRphysBase_MSR(i));
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state->mtrrs[i].mask = rdmsr(MTRRphysMask_MSR(i));
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}
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state->top_mem = rdmsr(TOP_MEM);
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state->top_mem = rdmsr(TOP_MEM);
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state->top_mem2 = rdmsr(TOP_MEM2);
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state->def_type = rdmsr(MTRRdefType_MSR);
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}
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@ -133,34 +133,33 @@ static void restore_mtrr_state(struct mtrr_state *state)
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int i;
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disable_cache();
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for(i = 0; i < MTRR_COUNT; i++) {
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for (i = 0; i < MTRR_COUNT; i++) {
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wrmsr(MTRRphysBase_MSR(i), state->mtrrs[i].base);
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wrmsr(MTRRphysMask_MSR(i), state->mtrrs[i].mask);
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}
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wrmsr(TOP_MEM, state->top_mem);
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wrmsr(TOP_MEM2, state->top_mem2);
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wrmsr(TOP_MEM, state->top_mem);
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wrmsr(TOP_MEM2, state->top_mem2);
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wrmsr(MTRRdefType_MSR, state->def_type);
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enable_cache();
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}
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#if 0
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static void print_mtrr_state(struct mtrr_state *state)
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{
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int i;
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for(i = 0; i < MTRR_COUNT; i++) {
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for (i = 0; i < MTRR_COUNT; i++) {
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printk(BIOS_DEBUG, "var mtrr %d: %08x%08x mask: %08x%08x\n",
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i,
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state->mtrrs[i].base.hi, state->mtrrs[i].base.lo,
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state->mtrrs[i].mask.hi, state->mtrrs[i].mask.lo);
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i,
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state->mtrrs[i].base.hi, state->mtrrs[i].base.lo,
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state->mtrrs[i].mask.hi, state->mtrrs[i].mask.lo);
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}
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printk(BIOS_DEBUG, "top_mem: %08x%08x\n",
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state->top_mem.hi, state->top_mem.lo);
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state->top_mem.hi, state->top_mem.lo);
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printk(BIOS_DEBUG, "top_mem2: %08x%08x\n",
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state->top_mem2.hi, state->top_mem2.lo);
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state->top_mem2.hi, state->top_mem2.lo);
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printk(BIOS_DEBUG, "def_type: %08x%08x\n",
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state->def_type.hi, state->def_type.lo);
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state->def_type.hi, state->def_type.lo);
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}
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#endif
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@ -171,7 +170,7 @@ static void set_init_ecc_mtrrs(void)
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disable_cache();
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/* First clear all of the msrs to be safe */
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for(i = 0; i < MTRR_COUNT; i++) {
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for (i = 0; i < MTRR_COUNT; i++) {
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msr_t zero;
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zero.lo = zero.hi = 0;
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wrmsr(MTRRphysBase_MSR(i), zero);
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@ -199,46 +198,47 @@ static void set_init_ecc_mtrrs(void)
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enable_cache();
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}
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static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_state)
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static inline void clear_2M_ram(unsigned long basek,
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struct mtrr_state *mtrr_state)
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{
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unsigned long limitk;
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unsigned long size;
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void *addr;
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unsigned long limitk;
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unsigned long size;
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void *addr;
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/* Report every 64M */
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if ((basek % (64*1024)) == 0) {
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/* Report every 64M */
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if ((basek % (64 * 1024)) == 0) {
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/* Restore the normal state */
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map_2M_page(0);
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restore_mtrr_state(mtrr_state);
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enable_lapic();
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/* Restore the normal state */
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map_2M_page(0);
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restore_mtrr_state(mtrr_state);
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enable_lapic();
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/* Print a status message */
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printk(BIOS_DEBUG, "%c", (basek >= TOLM_KB)?'+':'-');
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/* Print a status message */
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printk(BIOS_DEBUG, "%c", (basek >= TOLM_KB) ? '+' : '-');
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/* Return to the initialization state */
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set_init_ecc_mtrrs();
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disable_lapic();
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/* Return to the initialization state */
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set_init_ecc_mtrrs();
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disable_lapic();
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}
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}
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limitk = (basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1);
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limitk = (basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1);
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#if 0
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/* couldn't happen, memory must on 2M boundary */
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if(limitk>endk) {
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limitk = enk;
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}
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/* couldn't happen, memory must on 2M boundary */
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if (limitk > endk) {
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limitk = enk;
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}
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#endif
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size = (limitk - basek) << 10;
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addr = map_2M_page(basek >> 11);
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if (addr == MAPPING_ERROR) {
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printk(BIOS_ERR, "Cannot map page: %lx\n", basek >> 11);
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return;
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}
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size = (limitk - basek) << 10;
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addr = map_2M_page(basek >> 11);
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if (addr == MAPPING_ERROR) {
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printk(BIOS_ERR, "Cannot map page: %lx\n", basek >> 11);
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return;
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}
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/* clear memory 2M (limitk - basek) */
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addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10));
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memset(addr, 0, size);
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/* clear memory 2M (limitk - basek) */
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addr = (void *)(((uint32_t) addr) | ((basek & 0x7ff) << 10));
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memset(addr, 0, size);
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}
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static void init_ecc_memory(unsigned node_id)
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@ -271,14 +271,15 @@ static void init_ecc_memory(unsigned node_id)
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/* Enable cache scrubbing at the lowest possible rate */
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if (enable_scrubbing) {
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pci_write_config32(f3_dev, SCRUB_CONTROL,
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(SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_NONE << 0));
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(SCRUB_84ms << 16) | (SCRUB_84ms << 8) |
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(SCRUB_NONE << 0));
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} else {
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pci_write_config32(f3_dev, SCRUB_CONTROL,
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(SCRUB_NONE << 16) | (SCRUB_NONE << 8) | (SCRUB_NONE << 0));
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(SCRUB_NONE << 16) | (SCRUB_NONE << 8) |
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(SCRUB_NONE << 0));
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printk(BIOS_DEBUG, "Scrubbing Disabled\n");
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}
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/* If ecc support is not enabled don't touch memory */
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dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
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if (!(dcl & DCL_DimmEccEn)) {
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@ -286,32 +287,33 @@ static void init_ecc_memory(unsigned node_id)
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return;
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}
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startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2;
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endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
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startk =
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(pci_read_config32(f1_dev, 0x40 + (node_id * 8)) & 0xffff0000) >> 2;
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endk =
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((pci_read_config32(f1_dev, 0x44 + (node_id * 8)) & 0xffff0000) >>
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2) + 0x4000;
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#if CONFIG_HW_MEM_HOLE_SIZEK != 0
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unsigned long hole_startk = 0;
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#if CONFIG_K8_REV_F_SUPPORT == 0
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if (!is_cpu_pre_e0())
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{
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#endif
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uint32_t val;
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val = pci_read_config32(f1_dev, 0xf0);
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if(val & 1) {
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hole_startk = ((val & (0xff<<24)) >> 10);
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}
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#if CONFIG_K8_REV_F_SUPPORT == 0
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}
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#endif
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#if CONFIG_K8_REV_F_SUPPORT == 0
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if (!is_cpu_pre_e0()) {
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#endif
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uint32_t val;
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val = pci_read_config32(f1_dev, 0xf0);
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if (val & 1) {
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hole_startk = ((val & (0xff << 24)) >> 10);
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}
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#if CONFIG_K8_REV_F_SUPPORT == 0
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}
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#endif
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#endif
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/* Don't start too early */
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begink = startk;
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if (begink < (CONFIG_RAMTOP >> 10)) {
|
||||
begink = (CONFIG_RAMTOP >>10);
|
||||
begink = (CONFIG_RAMTOP >> 10);
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, "Clearing memory %luK - %luK: ", begink, endk);
|
||||
|
|
@ -326,26 +328,22 @@ static void init_ecc_memory(unsigned node_id)
|
|||
/* Walk through 2M chunks and zero them */
|
||||
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
|
||||
/* here hole_startk can not be equal to begink, never. Also hole_startk is in 2M boundary, 64M? */
|
||||
if ( (hole_startk != 0) && ((begink < hole_startk) && (endk>(4*1024*1024)))) {
|
||||
for(basek = begink; basek < hole_startk;
|
||||
basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
|
||||
{
|
||||
clear_2M_ram(basek, &mtrr_state);
|
||||
}
|
||||
for(basek = 4*1024*1024; basek < endk;
|
||||
basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
|
||||
{
|
||||
clear_2M_ram(basek, &mtrr_state);
|
||||
}
|
||||
}
|
||||
else
|
||||
if ((hole_startk != 0)
|
||||
&& ((begink < hole_startk) && (endk > (4 * 1024 * 1024)))) {
|
||||
for (basek = begink; basek < hole_startk;
|
||||
basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1))) {
|
||||
clear_2M_ram(basek, &mtrr_state);
|
||||
}
|
||||
for (basek = 4 * 1024 * 1024; basek < endk;
|
||||
basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1))) {
|
||||
clear_2M_ram(basek, &mtrr_state);
|
||||
}
|
||||
} else
|
||||
#endif
|
||||
for(basek = begink; basek < endk;
|
||||
basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
|
||||
{
|
||||
clear_2M_ram(basek, &mtrr_state);
|
||||
}
|
||||
|
||||
for (basek = begink; basek < endk;
|
||||
basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1))) {
|
||||
clear_2M_ram(basek, &mtrr_state);
|
||||
}
|
||||
|
||||
/* Restore the normal state */
|
||||
map_2M_page(0);
|
||||
|
|
@ -353,20 +351,20 @@ static void init_ecc_memory(unsigned node_id)
|
|||
enable_lapic();
|
||||
|
||||
/* Set the scrub base address registers */
|
||||
pci_write_config32(f3_dev, SCRUB_ADDR_LOW, startk << 10);
|
||||
pci_write_config32(f3_dev, SCRUB_ADDR_LOW, startk << 10);
|
||||
pci_write_config32(f3_dev, SCRUB_ADDR_HIGH, startk >> 22);
|
||||
|
||||
/* Enable the scrubber? */
|
||||
if (enable_scrubbing) {
|
||||
/* Enable scrubbing at the lowest possible rate */
|
||||
pci_write_config32(f3_dev, SCRUB_CONTROL,
|
||||
(SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_84ms << 0));
|
||||
(SCRUB_84ms << 16) | (SCRUB_84ms << 8) |
|
||||
(SCRUB_84ms << 0));
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, " done\n");
|
||||
}
|
||||
|
||||
|
||||
static inline void k8_errata(void)
|
||||
{
|
||||
msr_t msr;
|
||||
|
|
@ -384,7 +382,7 @@ static inline void k8_errata(void)
|
|||
|
||||
/* Erratum 81... */
|
||||
msr = rdmsr_amd(DC_CFG_MSR);
|
||||
msr.lo |= (1 << 10);
|
||||
msr.lo |= (1 << 10);
|
||||
wrmsr_amd(DC_CFG_MSR, msr);
|
||||
|
||||
}
|
||||
|
|
@ -432,12 +430,12 @@ static inline void k8_errata(void)
|
|||
msr.hi |= 1 << (43 - 32);
|
||||
wrmsr_amd(BU_CFG_MSR, msr);
|
||||
|
||||
if(is_cpu_d0()) {
|
||||
/* Erratum 110 ...*/
|
||||
if (is_cpu_d0()) {
|
||||
/* Erratum 110 ... */
|
||||
msr = rdmsr_amd(CPU_ID_HYPER_EXT_FEATURES);
|
||||
msr.hi |=1;
|
||||
msr.hi |= 1;
|
||||
wrmsr_amd(CPU_ID_HYPER_EXT_FEATURES, msr);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if CONFIG_K8_REV_F_SUPPORT == 0
|
||||
|
|
@ -445,9 +443,9 @@ static inline void k8_errata(void)
|
|||
#endif
|
||||
{
|
||||
/* Erratum 110 ... */
|
||||
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
|
||||
msr.hi |=1;
|
||||
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
|
||||
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
|
||||
msr.hi |= 1;
|
||||
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
|
||||
}
|
||||
|
||||
/* Erratum 122 */
|
||||
|
|
@ -456,10 +454,10 @@ static inline void k8_errata(void)
|
|||
wrmsr(HWCR_MSR, msr);
|
||||
|
||||
#if CONFIG_K8_REV_F_SUPPORT == 1
|
||||
/* Erratum 131... */
|
||||
msr = rdmsr(NB_CFG_MSR);
|
||||
msr.lo |= 1 << 20;
|
||||
wrmsr(NB_CFG_MSR, msr);
|
||||
/* Erratum 131... */
|
||||
msr = rdmsr(NB_CFG_MSR);
|
||||
msr.lo |= 1 << 20;
|
||||
wrmsr(NB_CFG_MSR, msr);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
|
@ -474,7 +472,7 @@ static void model_fxx_init(device_t dev)
|
|||
msr_t msr;
|
||||
struct node_core_id id;
|
||||
#if CONFIG_LOGICAL_CPUS == 1
|
||||
unsigned siblings;
|
||||
u32 siblings;
|
||||
#endif
|
||||
|
||||
#if CONFIG_K8_REV_F_SUPPORT == 1
|
||||
|
|
@ -484,7 +482,7 @@ static void model_fxx_init(device_t dev)
|
|||
#endif
|
||||
|
||||
#if CONFIG_USBDEBUG_DIRECT
|
||||
if(!ehci_debug_addr)
|
||||
if (!ehci_debug_addr)
|
||||
ehci_debug_addr = get_ehci_debug();
|
||||
set_ehci_debug(0);
|
||||
#endif
|
||||
|
|
@ -498,7 +496,7 @@ static void model_fxx_init(device_t dev)
|
|||
set_ehci_debug(ehci_debug_addr);
|
||||
#endif
|
||||
|
||||
/* Update the microcode */
|
||||
/* Update the microcode */
|
||||
model_fxx_update_microcode(dev->device);
|
||||
|
||||
disable_cache();
|
||||
|
|
@ -506,8 +504,8 @@ static void model_fxx_init(device_t dev)
|
|||
/* zero the machine check error status registers */
|
||||
msr.lo = 0;
|
||||
msr.hi = 0;
|
||||
for(i=0; i<5; i++) {
|
||||
wrmsr(MCI_STATUS + (i*4),msr);
|
||||
for (i = 0; i < 5; i++) {
|
||||
wrmsr(MCI_STATUS + (i * 4), msr);
|
||||
}
|
||||
|
||||
k8_errata();
|
||||
|
|
@ -526,34 +524,34 @@ static void model_fxx_init(device_t dev)
|
|||
setup_lapic();
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS == 1
|
||||
siblings = cpuid_ecx(0x80000008) & 0xff;
|
||||
siblings = cpuid_ecx(0x80000008) & 0xff;
|
||||
|
||||
if(siblings>0) {
|
||||
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
|
||||
msr.lo |= 1 << 28;
|
||||
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
|
||||
if (siblings > 0) {
|
||||
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
|
||||
msr.lo |= 1 << 28;
|
||||
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
|
||||
|
||||
msr = rdmsr_amd(LOGICAL_CPUS_NUM_MSR);
|
||||
msr.lo = (siblings+1)<<16;
|
||||
wrmsr_amd(LOGICAL_CPUS_NUM_MSR, msr);
|
||||
msr = rdmsr_amd(LOGICAL_CPUS_NUM_MSR);
|
||||
msr.lo = (siblings + 1) << 16;
|
||||
wrmsr_amd(LOGICAL_CPUS_NUM_MSR, msr);
|
||||
|
||||
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
|
||||
msr.hi |= 1<<(33-32);
|
||||
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
|
||||
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
|
||||
msr.hi |= 1 << (33 - 32);
|
||||
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
id = get_node_core_id(read_nb_cfg_54()); // pre e0 nb_cfg_54 can not be set
|
||||
id = get_node_core_id(read_nb_cfg_54()); // pre e0 nb_cfg_54 can not be set
|
||||
|
||||
/* Is this a bad location? In particular can another node prefecth
|
||||
* data from this node before we have initialized it?
|
||||
*/
|
||||
if (id.coreid == 0) init_ecc_memory(id.nodeid); // only do it for core 0
|
||||
if (id.coreid == 0)
|
||||
init_ecc_memory(id.nodeid); // only do it for core 0
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
/* Start up my cpu siblings */
|
||||
// if(id.coreid==0) amd_sibling_init(dev); // Don't need core1 is already be put in the CPU BUS in bus_cpu_scan
|
||||
/* Start up my cpu siblings */
|
||||
// if(id.coreid==0) amd_sibling_init(dev); // Don't need core1 is already be put in the CPU BUS in bus_cpu_scan
|
||||
#endif
|
||||
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue