Indent model_fxx_init and model_10xx_init.
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson
parent
ae60855f91
commit
c58f1d1df6
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@ -52,7 +52,6 @@ msr_t rdmsr_amd(u32 index)
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return result;
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}
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void wrmsr_amd(u32 index, msr_t msr)
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{
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__asm__ __volatile__(
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@ -62,7 +61,6 @@ void wrmsr_amd(u32 index, msr_t msr)
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);
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}
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static void model_10xxx_init(device_t dev)
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{
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u8 i;
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@ -89,7 +87,6 @@ static void model_10xxx_init(device_t dev)
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wrmsr(MCI_STATUS + (i * 4), msr);
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}
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enable_cache();
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/* Enable the local cpu apics */
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@ -128,6 +125,7 @@ static void model_10xxx_init(device_t dev)
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static struct device_operations cpu_dev_ops = {
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.init = model_10xxx_init,
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};
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static struct cpu_device_id cpu_table[] = {
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//AMD_GH_SUPPORT
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{ X86_VENDOR_AMD, 0x100f00 }, /* SH-F0 L1 */
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@ -144,6 +142,7 @@ static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */
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{ 0, 0 },
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};
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static const struct cpu_driver model_10xxx __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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@ -53,7 +53,8 @@ int is_e0_later_in_bsp(int nodeid)
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// d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
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device_t dev;
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dev = dev_find_slot(0, PCI_DEVFN(0x18 + nodeid, 2));
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if(!dev) return 0;
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if (!dev)
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return 0;
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val_old = pci_read_config32(dev, 0x80);
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val = val_old;
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val |= (1 << 3);
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@ -81,7 +82,7 @@ int is_cpu_f0_in_bsp(int nodeid)
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#define MCI_STATUS 0x401
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static inline msr_t rdmsr_amd(unsigned index)
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static inline msr_t rdmsr_amd(u32 index)
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{
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msr_t result;
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__asm__ __volatile__(
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@ -92,7 +93,7 @@ static inline msr_t rdmsr_amd(unsigned index)
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return result;
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}
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static inline void wrmsr_amd(unsigned index, msr_t msr)
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static inline void wrmsr_amd(u32 index, msr_t msr)
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{
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__asm__ __volatile__(
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"wrmsr"
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@ -101,7 +102,6 @@ static inline void wrmsr_amd(unsigned index, msr_t msr)
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);
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}
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#define MTRR_COUNT 8
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#define ZERO_CHUNK_KB 0x800UL /* 2M */
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#define TOLM_KB 0x400000UL
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@ -144,7 +144,6 @@ static void restore_mtrr_state(struct mtrr_state *state)
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enable_cache();
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}
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#if 0
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static void print_mtrr_state(struct mtrr_state *state)
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{
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@ -199,7 +198,8 @@ static void set_init_ecc_mtrrs(void)
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enable_cache();
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}
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static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_state)
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static inline void clear_2M_ram(unsigned long basek,
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struct mtrr_state *mtrr_state)
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{
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unsigned long limitk;
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unsigned long size;
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@ -271,14 +271,15 @@ static void init_ecc_memory(unsigned node_id)
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/* Enable cache scrubbing at the lowest possible rate */
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if (enable_scrubbing) {
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pci_write_config32(f3_dev, SCRUB_CONTROL,
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(SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_NONE << 0));
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(SCRUB_84ms << 16) | (SCRUB_84ms << 8) |
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(SCRUB_NONE << 0));
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} else {
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pci_write_config32(f3_dev, SCRUB_CONTROL,
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(SCRUB_NONE << 16) | (SCRUB_NONE << 8) | (SCRUB_NONE << 0));
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(SCRUB_NONE << 16) | (SCRUB_NONE << 8) |
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(SCRUB_NONE << 0));
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printk(BIOS_DEBUG, "Scrubbing Disabled\n");
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}
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/* If ecc support is not enabled don't touch memory */
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dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
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if (!(dcl & DCL_DimmEccEn)) {
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@ -286,15 +287,17 @@ static void init_ecc_memory(unsigned node_id)
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return;
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}
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startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2;
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endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
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startk =
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(pci_read_config32(f1_dev, 0x40 + (node_id * 8)) & 0xffff0000) >> 2;
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endk =
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((pci_read_config32(f1_dev, 0x44 + (node_id * 8)) & 0xffff0000) >>
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2) + 0x4000;
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#if CONFIG_HW_MEM_HOLE_SIZEK != 0
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unsigned long hole_startk = 0;
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#if CONFIG_K8_REV_F_SUPPORT == 0
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if (!is_cpu_pre_e0())
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{
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if (!is_cpu_pre_e0()) {
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#endif
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uint32_t val;
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@ -307,7 +310,6 @@ static void init_ecc_memory(unsigned node_id)
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#endif
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#endif
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/* Don't start too early */
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begink = startk;
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if (begink < (CONFIG_RAMTOP >> 10)) {
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@ -326,27 +328,23 @@ static void init_ecc_memory(unsigned node_id)
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/* Walk through 2M chunks and zero them */
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#if CONFIG_HW_MEM_HOLE_SIZEK != 0
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/* here hole_startk can not be equal to begink, never. Also hole_startk is in 2M boundary, 64M? */
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if ( (hole_startk != 0) && ((begink < hole_startk) && (endk>(4*1024*1024)))) {
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if ((hole_startk != 0)
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&& ((begink < hole_startk) && (endk > (4 * 1024 * 1024)))) {
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for (basek = begink; basek < hole_startk;
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basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
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{
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basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1))) {
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clear_2M_ram(basek, &mtrr_state);
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}
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for (basek = 4 * 1024 * 1024; basek < endk;
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basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
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{
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basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1))) {
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clear_2M_ram(basek, &mtrr_state);
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}
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}
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else
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} else
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#endif
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for (basek = begink; basek < endk;
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basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
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{
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basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1))) {
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clear_2M_ram(basek, &mtrr_state);
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}
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/* Restore the normal state */
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map_2M_page(0);
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restore_mtrr_state(&mtrr_state);
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@ -360,13 +358,13 @@ static void init_ecc_memory(unsigned node_id)
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if (enable_scrubbing) {
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/* Enable scrubbing at the lowest possible rate */
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pci_write_config32(f3_dev, SCRUB_CONTROL,
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(SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_84ms << 0));
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(SCRUB_84ms << 16) | (SCRUB_84ms << 8) |
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(SCRUB_84ms << 0));
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}
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printk(BIOS_DEBUG, " done\n");
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}
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static inline void k8_errata(void)
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{
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msr_t msr;
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@ -474,7 +472,7 @@ static void model_fxx_init(device_t dev)
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msr_t msr;
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struct node_core_id id;
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#if CONFIG_LOGICAL_CPUS == 1
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unsigned siblings;
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u32 siblings;
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#endif
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#if CONFIG_K8_REV_F_SUPPORT == 1
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@ -541,7 +539,6 @@ static void model_fxx_init(device_t dev)
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msr.hi |= 1 << (33 - 32);
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wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
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}
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#endif
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id = get_node_core_id(read_nb_cfg_54()); // pre e0 nb_cfg_54 can not be set
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@ -549,7 +546,8 @@ static void model_fxx_init(device_t dev)
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/* Is this a bad location? In particular can another node prefecth
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* data from this node before we have initialized it?
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*/
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if (id.coreid == 0) init_ecc_memory(id.nodeid); // only do it for core 0
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if (id.coreid == 0)
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init_ecc_memory(id.nodeid); // only do it for core 0
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#if CONFIG_LOGICAL_CPUS==1
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/* Start up my cpu siblings */
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