cpu/x86: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build and run on Galileo Gen2 Change-Id: I56ea28826963403dc0719f40c13782c56dc97feb Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18844 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
parent
8ca9a21a43
commit
c5917079eb
|
@ -127,7 +127,8 @@ void udelay(u32 usecs)
|
|||
timer_fsb = get_timer_fsb();
|
||||
}
|
||||
|
||||
/* Calculate the number of ticks to run, our FSB runs at timer_fsb Mhz */
|
||||
/* Calculate the number of ticks to run, our FSB runs at timer_fsb Mhz
|
||||
*/
|
||||
ticks = usecs * timer_fsb;
|
||||
start = lapic_read(LAPIC_TMCCT);
|
||||
do {
|
||||
|
|
|
@ -5,7 +5,8 @@
|
|||
* Copyright (C) 2001 Ronald G. Minnich
|
||||
* Copyright (C) 2005 Yinghai Lu
|
||||
* Copyright (C) 2008 coresystems GmbH
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,
|
||||
* Raptor Engineering
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
@ -74,7 +75,8 @@ static void copy_secondary_start_to_lowest_1M(void)
|
|||
/* Fill in secondary_start's local gdt. */
|
||||
setup_secondary_gdt();
|
||||
|
||||
code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
|
||||
code_size = (unsigned long)_secondary_start_end
|
||||
- (unsigned long)_secondary_start;
|
||||
|
||||
if (acpi_is_wakeup_s3()) {
|
||||
/* need to save it for RAM resume */
|
||||
|
@ -89,7 +91,8 @@ static void copy_secondary_start_to_lowest_1M(void)
|
|||
}
|
||||
|
||||
/* copy the _secondary_start to the RAM below 1M*/
|
||||
memcpy((unsigned char *)AP_SIPI_VECTOR, (unsigned char *)_secondary_start, code_size);
|
||||
memcpy((unsigned char *)AP_SIPI_VECTOR,
|
||||
(unsigned char *)_secondary_start, code_size);
|
||||
|
||||
printk(BIOS_DEBUG, "start_eip=0x%08lx, code_size=0x%08lx\n",
|
||||
(long unsigned int)AP_SIPI_VECTOR, code_size);
|
||||
|
@ -145,7 +148,8 @@ static int lapic_start_cpu(unsigned long apicid)
|
|||
}
|
||||
return 0;
|
||||
}
|
||||
#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_INTEL_MODEL_206AX && !CONFIG_CPU_INTEL_MODEL_2065X
|
||||
#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_INTEL_MODEL_206AX \
|
||||
&& !CONFIG_CPU_INTEL_MODEL_2065X
|
||||
mdelay(10);
|
||||
#endif
|
||||
|
||||
|
|
|
@ -17,7 +17,8 @@
|
|||
* GNU General Public License for more details.
|
||||
*
|
||||
*
|
||||
* Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming
|
||||
* Reference: Intel Architecture Software Developer's Manual, Volume 3: System
|
||||
* Programming
|
||||
*/
|
||||
|
||||
#include <stddef.h>
|
||||
|
@ -198,8 +199,8 @@ static struct memranges *get_physical_address_space(void)
|
|||
* resources are appropriate for this MTRR type. */
|
||||
match = IORESOURCE_PREFETCH;
|
||||
mask |= match;
|
||||
memranges_add_resources_filter(addr_space, mask, match, MTRR_TYPE_WRCOMB,
|
||||
filter_vga_wrcomb);
|
||||
memranges_add_resources_filter(addr_space, mask, match,
|
||||
MTRR_TYPE_WRCOMB, filter_vga_wrcomb);
|
||||
|
||||
/* The address space below 4GiB is special. It needs to be
|
||||
* covered entirely by range entries so that MTRR calculations
|
||||
|
|
|
@ -65,7 +65,8 @@ void *map_2M_page(unsigned long page)
|
|||
struct pde pdp[512];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
static struct pg_table pgtbl[CONFIG_MAX_CPUS] __attribute__ ((aligned(4096)));
|
||||
static struct pg_table pgtbl[CONFIG_MAX_CPUS]
|
||||
__attribute__ ((aligned(4096)));
|
||||
static unsigned long mapped_window[CONFIG_MAX_CPUS];
|
||||
unsigned long index;
|
||||
unsigned long window;
|
||||
|
@ -79,7 +80,9 @@ void *map_2M_page(unsigned long page)
|
|||
paging_off();
|
||||
if (window > 1) {
|
||||
struct pde *pd, *pdp;
|
||||
/* Point the page directory pointers at the page directories */
|
||||
/* Point the page directory pointers at the page
|
||||
* directories
|
||||
*/
|
||||
memset(&pgtbl[index].pdp, 0, sizeof(pgtbl[index].pdp));
|
||||
pd = pgtbl[index].pd;
|
||||
pdp = pgtbl[index].pdp;
|
||||
|
@ -87,14 +90,18 @@ void *map_2M_page(unsigned long page)
|
|||
pdp[1].addr_lo = ((uint32_t)&pd[512*1])|1;
|
||||
pdp[2].addr_lo = ((uint32_t)&pd[512*2])|1;
|
||||
pdp[3].addr_lo = ((uint32_t)&pd[512*3])|1;
|
||||
/* The first half of the page table is identity mapped */
|
||||
/* The first half of the page table is identity mapped
|
||||
*/
|
||||
for (i = 0; i < 1024; i++) {
|
||||
pd[i].addr_lo = ((i & 0x3ff) << 21) | 0xE3;
|
||||
pd[i].addr_hi = 0;
|
||||
}
|
||||
/* The second half of the page table holds the mapped page */
|
||||
/* The second half of the page table holds the mapped
|
||||
* page
|
||||
*/
|
||||
for (i = 1024; i < 2048; i++) {
|
||||
pd[i].addr_lo = ((window & 1) << 31) | ((i & 0x3ff) << 21) | 0xE3;
|
||||
pd[i].addr_lo = ((window & 1) << 31)
|
||||
| ((i & 0x3ff) << 21) | 0xE3;
|
||||
pd[i].addr_hi = (window >> 1);
|
||||
}
|
||||
paging_on(pdp);
|
||||
|
|
|
@ -131,7 +131,10 @@ void smi_handler(u32 smm_revision)
|
|||
*/
|
||||
while (smi_handler_status == SMI_LOCKED) {
|
||||
asm volatile (
|
||||
".byte 0xf3, 0x90\n" /* hint a CPU we are in spinlock (PAUSE instruction, REP NOP) */
|
||||
".byte 0xf3, 0x90\n" /* hint a CPU we are in
|
||||
* spinlock (PAUSE
|
||||
* instruction, REP NOP)
|
||||
*/
|
||||
);
|
||||
}
|
||||
return;
|
||||
|
@ -203,9 +206,12 @@ void smi_handler(u32 smm_revision)
|
|||
* weak relocations w/o a symbol have a 0 address which is where the modules
|
||||
* are linked at. */
|
||||
int __attribute__((weak)) mainboard_io_trap_handler(int smif) { return 0; }
|
||||
void __attribute__((weak)) cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save) {}
|
||||
void __attribute__((weak)) northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) {}
|
||||
void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) {}
|
||||
void __attribute__((weak)) cpu_smi_handler(unsigned int node,
|
||||
smm_state_save_area_t *state_save) {}
|
||||
void __attribute__((weak)) northbridge_smi_handler(unsigned int node,
|
||||
smm_state_save_area_t *state_save) {}
|
||||
void __attribute__((weak)) southbridge_smi_handler(unsigned int node,
|
||||
smm_state_save_area_t *state_save) {}
|
||||
void __attribute__((weak)) mainboard_smi_gpi(u32 gpi_sts) {}
|
||||
int __attribute__((weak)) mainboard_smi_apmc(u8 data) { return 0; }
|
||||
void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ) {}
|
||||
|
|
|
@ -141,7 +141,8 @@ untampered_lapic:
|
|||
/* This is an ugly hack, and we should find a way to read the CPU index
|
||||
* without relying on the LAPIC ID.
|
||||
*/
|
||||
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) || IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_RL)
|
||||
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) \
|
||||
|| IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_RL)
|
||||
/* LAPIC IDs start from 0x10; map that to the proper core index */
|
||||
subl $0x10, %ecx
|
||||
#endif
|
||||
|
|
|
@ -47,7 +47,8 @@ static unsigned long calibrate_tsc_with_pit(void)
|
|||
* (interrupt on terminal count mode), binary count,
|
||||
* load 5 * LATCH count, (LSB and MSB) to begin countdown.
|
||||
*/
|
||||
outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
|
||||
outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
|
||||
|
||||
outb(CALIBRATE_INTERVAL & 0xff, 0x42); /* LSB of count */
|
||||
outb(CALIBRATE_INTERVAL >> 8, 0x42); /* MSB of count */
|
||||
|
||||
|
|
Loading…
Reference in New Issue