GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

peppy: Set optimal DTLE register values 

Empirical testing shows that 0x5 is the optimal setting for DTLE DATA /
EDGE on Peppy.

Change-Id: I273a3a68be97b3eb7c2ee2071e5de1ef7bf7f2d9
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65717
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4476
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Shawn Nematbakhsh 2013-08-13 10:50:15 -07:00 committed by Patrick Georgi
parent 287522749e
commit c59fda3216
1 changed files with 4 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/google/peppy/devicetree.cb
View File

@ -70,6 +70,10 @@ chip northbridge/intel/haswell
register "sata_ahci" = "0x1" register "sata_ahci" = "0x1"
register "sata_port_map" = "0x1" register "sata_port_map" = "0x1"
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
register "sata_port1_gen3_dtle" = "0x5"
register "sio_acpi_mode" = "0" register "sio_acpi_mode" = "0"
register "sio_i2c0_voltage" = "0" # 3.3V register "sio_i2c0_voltage" = "0" # 3.3V
register "sio_i2c1_voltage" = "0" # 3.3V register "sio_i2c1_voltage" = "0" # 3.3V