[REMOVAL] tyan/s2882
As announced in http://permalink.gmane.org/gmane.linux.bios/81918 I am removing all boards older than 10 years from the tree. Change-Id: Ie44a3c46b82e77028921339c50ae4c176e38055c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12379 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Stefan Reinauer
parent
3844d9a30c
commit
c5ab0979f6
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@ -1,50 +0,0 @@
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if BOARD_TYAN_S2882
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_AMD_SOCKET_940
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select NORTHBRIDGE_AMD_AMDK8
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select SOUTHBRIDGE_AMD_AMD8131
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select SOUTHBRIDGE_AMD_AMD8111
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select SUPERIO_WINBOND_W83627HF
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select BOARD_ROMSIZE_KB_512
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select SB_HT_CHAIN_UNITID_OFFSET_ONLY
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select DRIVERS_SIL_3114
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select QRANK_DIMM_SUPPORT
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config MAINBOARD_DIR
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string
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default tyan/s2882
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config APIC_ID_OFFSET
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hex
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default 0x0
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config MAINBOARD_PART_NUMBER
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string
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default "S2882"
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config MAX_CPUS
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int
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default 4
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config MAX_PHYSICAL_CPUS
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int
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default 2
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config HT_CHAIN_UNITID_BASE
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hex
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default 0x1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x20
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config IRQ_SLOT_COUNT
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int
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default 15
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endif # BOARD_TYAN_S2882
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@ -1,2 +0,0 @@
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config BOARD_TYAN_S2882
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bool "S2882 (Thunder K8S Pro)"
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@ -1,5 +0,0 @@
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Board name: Thunder K8S Pro (S2882)
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Category: server
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Board URL: http://www.tyan.com/archive/products/html/thunderk8spro.html
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Flashrom support: y
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Release year: 2003
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@ -1,60 +0,0 @@
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entries
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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395 1 e 1 hw_scrubber
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396 1 e 1 interleave_chip_selects
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397 2 e 8 max_mem_clock
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399 1 e 2 multi_core
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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440 4 e 9 slow_cpu
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444 1 e 1 nmi
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445 1 e 1 iommu
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456 1 e 1 ECC_memory
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728 256 h 0 user_data
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984 16 h 0 check_sum
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# Reserve the extended AMD configuration registers
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1000 24 r 0 amd_reserved
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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8 0 DDR400
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8 1 DDR333
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8 2 DDR266
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8 3 DDR200
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9 0 off
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9 1 87.5%
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9 2 75.0%
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9 3 62.5%
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9 4 50.0%
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9 5 37.5%
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9 6 25.0%
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9 7 12.5%
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checksums
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checksum 392 983 984
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@ -1,125 +0,0 @@
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chip northbridge/amd/amdk8/root_complex
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device cpu_cluster 0 on
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chip cpu/amd/socket_940
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device lapic 0 on end
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end
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end
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device domain 0 on
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subsystemid 0x10f1 0x2882 inherit
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chip northbridge/amd/amdk8
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device pci 18.0 on # northbridge
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# devices on link 0, link 0 == LDT 0
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chip southbridge/amd/amd8131
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# the on/off keyword is mandatory
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device pci 0.0 on
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device pci 6.0 on end # adaptec
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device pci 6.1 on end
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device pci 9.0 on end # broadcom 5704
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device pci 9.1 on end
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end
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device pci 0.1 on end
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device pci 1.0 on end
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device pci 1.1 on end
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end
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chip southbridge/amd/amd8111
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# this "device pci 0.0" is the parent the next one
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# PCI bridge
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device pci 0.0 on
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 0.2 off end
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device pci 1.0 off end
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device pci 5.0 on end
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# chip drivers/ati/ragexl
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device pci 6.0 on end
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# end
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device pci 8.0 on end #intel 10/100
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end
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device pci 1.0 on
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chip superio/winbond/w83627hf
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.6 off # CIR
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io 0x60 = 0x100
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end
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device pnp 2e.7 off # GAME_MIDI_GIPO1
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io 0x60 = 0x220
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io 0x62 = 0x300
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irq 0x70 = 9
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end
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device pnp 2e.8 off end # GPIO2
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device pnp 2e.9 off end # GPIO3
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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irq 0x70 = 5
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end
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end
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end
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device pci 1.1 on end
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device pci 1.2 on end
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device pci 1.3 on end
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device pci 1.3 on
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# chip drivers/generic/generic #dimm 0-0-0
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# device i2c 50 on end
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# end
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# chip drivers/generic/generic #dimm 0-0-1
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# device i2c 51 on end
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# end
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# chip drivers/generic/generic #dimm 0-1-0
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# device i2c 52 on end
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# end
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# chip drivers/generic/generic #dimm 0-1-1
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# device i2c 53 on end
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# end
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# chip drivers/generic/generic #dimm 1-0-0
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# device i2c 54 on end
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# end
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# chip drivers/generic/generic #dimm 1-0-1
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# device i2c 55 on end
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# end
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# chip drivers/generic/generic #dimm 1-1-0
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# device i2c 56 on end
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# end
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# chip drivers/generic/generic #dimm 1-1-1
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# device i2c 57 on end
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# end
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end # acpi
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device pci 1.5 off end
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device pci 1.6 off end
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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end
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end # device pci 18.0
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device pci 18.0 on end
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device pci 18.0 on end
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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end # NB
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end #domain
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end
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@ -1,243 +0,0 @@
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#include <console/console.h>
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#include <device/pci.h>
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#include <string.h>
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#include <stdint.h>
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#include <arch/pirq_routing.h>
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static unsigned node_link_to_bus(unsigned node, unsigned link)
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{
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device_t dev;
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unsigned reg;
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dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
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if (!dev) {
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return 0;
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}
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for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
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uint32_t config_map;
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unsigned dst_node;
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unsigned dst_link;
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unsigned bus_base;
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config_map = pci_read_config32(dev, reg);
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if ((config_map & 3) != 3) {
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continue;
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}
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dst_node = (config_map >> 4) & 7;
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dst_link = (config_map >> 8) & 3;
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bus_base = (config_map >> 16) & 0xff;
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if ((dst_node == node) && (dst_link == link))
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{
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return bus_base;
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}
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}
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return 0;
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}
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static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
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uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
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uint8_t slot, uint8_t rfu)
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{
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pirq_info->bus = bus;
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pirq_info->devfn = devfn;
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pirq_info->irq[0].link = link0;
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pirq_info->irq[0].bitmap = bitmap0;
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pirq_info->irq[1].link = link1;
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pirq_info->irq[1].bitmap = bitmap1;
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pirq_info->irq[2].link = link2;
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pirq_info->irq[2].bitmap = bitmap2;
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pirq_info->irq[3].link = link3;
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pirq_info->irq[3].bitmap = bitmap3;
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pirq_info->slot = slot;
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pirq_info->rfu = rfu;
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}
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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struct irq_routing_table *pirq;
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struct irq_info *pirq_info;
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unsigned slot_num;
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uint8_t *v;
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uint8_t sum=0;
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int i;
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unsigned char bus_chain_0;
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unsigned char bus_8131_1;
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unsigned char bus_8131_2;
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unsigned char bus_8111_1;
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{
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device_t dev;
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/* HT chain 0 */
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bus_chain_0 = node_link_to_bus(0, 0);
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if (bus_chain_0 == 0) {
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printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
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bus_chain_0 = 1;
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}
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/* 8111 */
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dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
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if (dev) {
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bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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else {
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printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
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bus_8111_1 = 4;
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}
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/* 8131-1 */
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dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
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if (dev) {
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bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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else {
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printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
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bus_8131_1 = 2;
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}
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/* 8131-2 */
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dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
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if (dev) {
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bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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else {
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printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
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bus_8131_2 = 3;
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}
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}
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/* Align the table to be 16 byte aligned. */
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addr += 15;
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addr &= ~15;
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/* This table must be between 0xf0000 & 0x100000 */
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printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...\n", addr);
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pirq = (void *)(addr);
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v = (uint8_t *)(addr);
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pirq->signature = PIRQ_SIGNATURE;
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pirq->version = PIRQ_VERSION;
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pirq->rtr_bus = bus_chain_0;
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pirq->rtr_devfn = (4<<3)|3;
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pirq->exclusive_irqs = 0;
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pirq->rtr_vendor = 0x1022;
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pirq->rtr_device = 0x746b;
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pirq->miniport_data = 0;
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memset(pirq->rfu, 0, sizeof(pirq->rfu));
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pirq_info = (void *) ( &pirq->checksum + 1);
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slot_num = 0;
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{
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device_t dev;
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dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x04,3));
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if (dev) {
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/* initialize PCI interupts - these assignments depend
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on the PCB routing of PINTA-D
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PINTA = IRQ5
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PINTB = IRQ9
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PINTC = IRQ11
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PINTD = IRQ10
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*/
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pci_write_config16(dev, 0x56, 0xab95);
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}
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}
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printk(BIOS_DEBUG, "setting Onboard AMD Southbridge\n");
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static const unsigned char slotIrqs_1_4[4] = { 5, 9, 11, 10 };
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pci_assign_irqs(bus_chain_0, 4, slotIrqs_1_4);
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write_pirq_info(pirq_info, bus_chain_0,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
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pirq_info++; slot_num++;
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printk(BIOS_DEBUG, "setting Onboard AMD USB\n");
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static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 10 };
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pci_assign_irqs(bus_8111_1, 0, slotIrqs_8111_1_0);
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write_pirq_info(pirq_info, bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0);
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pirq_info++; slot_num++;
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printk(BIOS_DEBUG, "setting Onboard ATI Display Adapter\n");
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static const unsigned char slotIrqs_8111_1_6[4] = { 11, 0, 0, 0 };
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pci_assign_irqs(bus_8111_1, 6, slotIrqs_8111_1_6);
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write_pirq_info(pirq_info, bus_8111_1,(6<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
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pirq_info++; slot_num++;
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printk(BIOS_DEBUG, "setting Slot 1\n");
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static const unsigned char slotIrqs_8131_2_3[4] = { 5, 9, 11, 10 };
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pci_assign_irqs(bus_8131_2, 3, slotIrqs_8131_2_3);
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write_pirq_info(pirq_info, bus_8131_2,(3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0);
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pirq_info++; slot_num++;
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printk(BIOS_DEBUG, "setting Slot 2\n");
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static const unsigned char slotIrqs_8131_2_1[4] = { 9, 11, 10, 5 };
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pci_assign_irqs(bus_8131_2, 1, slotIrqs_8131_2_1);
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write_pirq_info(pirq_info, bus_8131_2,(1<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0);
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pirq_info++; slot_num++;
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printk(BIOS_DEBUG, "setting Slot 3\n");
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static const unsigned char slotIrqs_8131_1_3[4] = { 10, 5, 9, 11 };
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pci_assign_irqs(bus_8131_1, 3, slotIrqs_8131_1_3);
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write_pirq_info(pirq_info, bus_8131_1,(3<<3)|0, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x3, 0);
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pirq_info++; slot_num++;
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printk(BIOS_DEBUG, "setting Slot 4\n");
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static const unsigned char slotIrqs_8131_1_2[4] = { 11, 10, 5, 9 };
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pci_assign_irqs(bus_8131_1, 2, slotIrqs_8131_1_2);
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write_pirq_info(pirq_info, bus_8131_1,(2<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x4, 0);
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pirq_info++; slot_num++;
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printk(BIOS_DEBUG, "setting Slot 5\n");
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static const unsigned char slotIrqs_8111_1_4[4] = { 5, 9, 11, 10 };
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pci_assign_irqs(bus_8111_1, 4, slotIrqs_8111_1_4);
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write_pirq_info(pirq_info, bus_8111_1,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x5, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
printk(BIOS_DEBUG, "setting Onboard SI Serial ATA\n");
|
||||
static const unsigned char slotIrqs_8111_1_5[4] = { 10, 0, 0, 0 };
|
||||
pci_assign_irqs(bus_8111_1, 5, slotIrqs_8111_1_5);
|
||||
write_pirq_info(pirq_info, bus_8111_1,(5<<3)|0, 0x4, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
printk(BIOS_DEBUG, "setting Onboard Intel NIC\n");
|
||||
static const unsigned char slotIrqs_8111_1_8[4] = { 11, 0, 0, 0 };
|
||||
pci_assign_irqs(bus_8111_1, 8, slotIrqs_8111_1_8);
|
||||
write_pirq_info(pirq_info, bus_8111_1,(8<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
printk(BIOS_DEBUG, "setting Onboard Adaptec SCSI\n");
|
||||
static const unsigned char slotIrqs_8131_1_6[4] = { 5, 9, 0, 0 };
|
||||
pci_assign_irqs(bus_8131_1, 6, slotIrqs_8131_1_6);
|
||||
write_pirq_info(pirq_info, bus_8131_1,(6<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
printk(BIOS_DEBUG, "setting Onboard Broadcom NIC\n");
|
||||
static const unsigned char slotIrqs_8131_1_9[4] = { 5, 9, 0, 0 };
|
||||
pci_assign_irqs(bus_8131_1, 9, slotIrqs_8131_1_9);
|
||||
write_pirq_info(pirq_info, bus_8131_1,(9<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "done.\n");
|
||||
|
||||
return (unsigned long) pirq_info;
|
||||
}
|
||||
|
|
@ -1,220 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#if CONFIG_LOGICAL_CPUS
|
||||
#include <cpu/amd/multicore.h>
|
||||
#endif
|
||||
|
||||
static unsigned node_link_to_bus(unsigned node, unsigned link)
|
||||
{
|
||||
device_t dev;
|
||||
unsigned reg;
|
||||
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
|
||||
if (!dev) {
|
||||
return 0;
|
||||
}
|
||||
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
|
||||
uint32_t config_map;
|
||||
unsigned dst_node;
|
||||
unsigned dst_link;
|
||||
unsigned bus_base;
|
||||
config_map = pci_read_config32(dev, reg);
|
||||
if ((config_map & 3) != 3) {
|
||||
continue;
|
||||
}
|
||||
dst_node = (config_map >> 4) & 7;
|
||||
dst_link = (config_map >> 8) & 3;
|
||||
bus_base = (config_map >> 16) & 0xff;
|
||||
#if 0
|
||||
printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
|
||||
dst_node, dst_link, bus_base,
|
||||
reg, config_map);
|
||||
#endif
|
||||
if ((dst_node == node) && (dst_link == link))
|
||||
{
|
||||
return bus_base;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
unsigned char bus_chain_0;
|
||||
unsigned char bus_8131_1;
|
||||
unsigned char bus_8131_2;
|
||||
unsigned char bus_8111_1;
|
||||
unsigned apicid_base;
|
||||
unsigned apicid_8111;
|
||||
unsigned apicid_8131_1;
|
||||
unsigned apicid_8131_2;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
/* HT chain 0 */
|
||||
bus_chain_0 = node_link_to_bus(0, 0);
|
||||
if (bus_chain_0 == 0) {
|
||||
printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
|
||||
bus_chain_0 = 1;
|
||||
}
|
||||
|
||||
/* 8111 */
|
||||
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
|
||||
if (dev) {
|
||||
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
|
||||
|
||||
bus_8111_1 = 4;
|
||||
}
|
||||
/* 8131-1 */
|
||||
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
|
||||
if (dev) {
|
||||
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
|
||||
|
||||
bus_8131_1 = 2;
|
||||
}
|
||||
/* 8131-2 */
|
||||
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
|
||||
if (dev) {
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
|
||||
|
||||
bus_8131_2 = 3;
|
||||
}
|
||||
}
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
#if CONFIG_LOGICAL_CPUS
|
||||
apicid_base = get_apicid_base(3);
|
||||
#else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
#endif
|
||||
apicid_8111 = apicid_base+0;
|
||||
apicid_8131_1 = apicid_base+1;
|
||||
apicid_8131_2 = apicid_base+2;
|
||||
|
||||
smp_write_ioapic(mc, apicid_8111, 0x11, VIO_APIC_VADDR);
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_8131_1, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_8131_2, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
|
||||
|
||||
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|3, apicid_8111, 0x13);
|
||||
|
||||
|
||||
//On Board AMD USB
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
|
||||
|
||||
|
||||
//On Board ATI Display Adapter
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
|
||||
|
||||
#if 1
|
||||
//Slot 5 PCI 32
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, apicid_8111, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); //
|
||||
|
||||
#endif
|
||||
//Onboard SI Serial ATA
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x13);
|
||||
|
||||
//Onboard Intel 82551 10/100M NIC
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (8<<2)|0, apicid_8111, 0x12);
|
||||
|
||||
#if 1
|
||||
//Slot 3 PCIX 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, apicid_8131_1, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);//
|
||||
|
||||
//Slot 4 PCIX 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, apicid_8131_1, 0x1);//
|
||||
|
||||
|
||||
#endif
|
||||
//Onboard adaptec scsi
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|0, apicid_8131_1, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|1, apicid_8131_1, 0x1);
|
||||
|
||||
//On Board NIC
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1);
|
||||
|
||||
|
||||
#if 1
|
||||
//Slot 1 PCI-X 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); //
|
||||
|
||||
//Slot 2 PCI-X 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, apicid_8131_2, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, apicid_8131_2, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, apicid_8131_2, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);//
|
||||
|
||||
#endif
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
mptable_lintsrc(mc, bus_isa);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
|
@ -1,116 +0,0 @@
|
|||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <stdlib.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <console/console.h>
|
||||
#include <lib.h>
|
||||
#include <spd.h>
|
||||
#include <cpu/amd/model_fxx_rev.h>
|
||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||
#include "southbridge/amd/amd8111/early_smbus.c"
|
||||
#include <northbridge/amd/amdk8/raminit.h>
|
||||
#include <delay.h>
|
||||
#include "northbridge/amd/amdk8/reset_test.c"
|
||||
#include "northbridge/amd/amdk8/debug.c"
|
||||
#include <superio/winbond/common/winbond.h>
|
||||
#include <superio/winbond/w83627hf/w83627hf.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
#include "southbridge/amd/amd8111/early_ctrl.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
if (is_cpu_pre_c0())
|
||||
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
|
||||
else
|
||||
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
|
||||
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
|
||||
}
|
||||
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
if (is_cpu_pre_c0()) {
|
||||
udelay(800);
|
||||
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
|
||||
udelay(90);
|
||||
}
|
||||
}
|
||||
|
||||
static void activate_spd_rom(const struct mem_controller *ctrl) { }
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
#include "northbridge/amd/amdk8/resourcemap.c"
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
#include "cpu/amd/dualcore/dualcore.c"
|
||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
static const struct mem_controller cpu[] = {
|
||||
{
|
||||
.node_id = 0,
|
||||
.f0 = PCI_DEV(0, 0x18, 0),
|
||||
.f1 = PCI_DEV(0, 0x18, 1),
|
||||
.f2 = PCI_DEV(0, 0x18, 2),
|
||||
.f3 = PCI_DEV(0, 0x18, 3),
|
||||
.channel0 = { DIMM0, DIMM2, 0, 0 },
|
||||
.channel1 = { DIMM1, DIMM3, 0, 0 },
|
||||
},
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
||||
{
|
||||
.node_id = 1,
|
||||
.f0 = PCI_DEV(0, 0x19, 0),
|
||||
.f1 = PCI_DEV(0, 0x19, 1),
|
||||
.f2 = PCI_DEV(0, 0x19, 2),
|
||||
.f3 = PCI_DEV(0, 0x19, 3),
|
||||
.channel0 = { DIMM4, DIMM6, 0, 0 },
|
||||
.channel1 = { DIMM5, DIMM7, 0, 0 },
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
int needs_reset;
|
||||
|
||||
if (bist == 0)
|
||||
init_cpus(cpu_init_detectedx);
|
||||
|
||||
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
setup_default_resource_map();
|
||||
|
||||
needs_reset = setup_coherent_ht_domain();
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS
|
||||
// It is said that we should start core1 after all core0 launched
|
||||
start_other_cores();
|
||||
#endif
|
||||
// automatically set that for you, but you might meet tight space
|
||||
needs_reset |= ht_setup_chains_x();
|
||||
|
||||
if (needs_reset) {
|
||||
printk(BIOS_INFO, "ht reset -\n");
|
||||
soft_reset();
|
||||
}
|
||||
|
||||
enable_smbus();
|
||||
|
||||
memreset_setup();
|
||||
sdram_initialize(ARRAY_SIZE(cpu), cpu);
|
||||
|
||||
post_cache_as_ram();
|
||||
}
|
||||
Loading…
Reference in New Issue