soc/mediatek/mt8186: Fix issue of clearing watchdog status

The implementation of clearing watchdog status is wrong in CB:58835.
The value written to the 'wdt_mode' register should be
'wdt_mode | 0x22000000' instead of 'wdt_status | 0x22000000'.

BUG=b:204229208
TEST=check watchdog status is cleared.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I8c5dbaab2ac43d3867037bc4160aa5af2d79284f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Rex-BC Chen 2022-01-28 17:38:29 +08:00 committed by Hung-Te Lin
parent 5c7a923757
commit c5ab260cbd
4 changed files with 10 additions and 7 deletions

View File

@ -39,6 +39,6 @@ enum {
static struct mtk_wdt_regs *const mtk_wdt = (void *)RGU_BASE;
int mtk_wdt_init(void);
void mtk_wdt_clr_status(uint32_t wdt_sta);
void mtk_wdt_clr_status(void);
#endif /* SOC_MEDIATEK_COMMON_WDT_H */

View File

@ -6,7 +6,7 @@
#include <soc/wdt.h>
#include <vendorcode/google/chromeos/chromeos.h>
__weak void mtk_wdt_clr_status(uint32_t wdt_sta) { /* do nothing */ }
__weak void mtk_wdt_clr_status(void) { /* do nothing */ }
int mtk_wdt_init(void)
{
@ -15,7 +15,7 @@ int mtk_wdt_init(void)
/* Writing mode register will clear status register */
wdt_sta = read32(&mtk_wdt->wdt_status);
mtk_wdt_clr_status(wdt_sta);
mtk_wdt_clr_status();
printk(BIOS_INFO, "WDT: Status = %#x\n", wdt_sta);

View File

@ -9,9 +9,12 @@
#include <soc/addressmap.h>
#include <soc/wdt.h>
#define MTK_WDT_CLR_STATUS 0x22000000
#define MTK_WDT_CLR_STATUS_VAL 0x22
void mtk_wdt_clr_status(uint32_t wdt_sta)
DEFINE_BITFIELD(MTK_WDT_CLR_STATUS, 31, 24)
void mtk_wdt_clr_status(void)
{
write32(&mtk_wdt->wdt_mode, wdt_sta | MTK_WDT_CLR_STATUS);
SET32_BITFIELDS(&mtk_wdt->wdt_mode,
MTK_WDT_CLR_STATUS, MTK_WDT_CLR_STATUS_VAL);
}

View File

@ -6,7 +6,7 @@
#define MTK_WDT_CLR_STATUS 0x230001FF
void mtk_wdt_clr_status(uint32_t wdt_sta)
void mtk_wdt_clr_status(void)
{
write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS);
}