try to get memory mapped i/o to work
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -4,18 +4,30 @@
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uses PCIC0_CFGADDR
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uses PCIC0_CFGDATA
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uses UART0_IO_BASE
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uses ISA_IO_BASE
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uses ISA_MEM_BASE
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uses TTYS0_BASE
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uses _IO_BASE
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##
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## Set PCI registers
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## Set PCI configuration register addresses
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##
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default PCIC0_CFGADDR=0xeec00000
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default PCIC0_CFGDATA=0xeec00004
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##
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## Set UART base address
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## Set PCI/ISA I/O and memory base address
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##
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default UART0_IO_BASE=0xef600300
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default ISA_IO_BASE=0xe8000000
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default ISA_MEM_BASE=0x80000000
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default _IO_BASE=ISA_IO_BASE
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##
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## HACK ALERT: the UART0 registers are not in the PCI I/O address space
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## but both IDE and UART use the same routines for I/O (inb/outb). To get
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## around this we set TTYSO_BASE to the difference between the two.
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##
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default TTYS0_BASE=0xef600300-ISA_IO_BASE
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##
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## Early board initialization, called from ppc_main()
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@ -54,21 +54,21 @@ board_init(void)
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/*
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* Enable FLASH, NVRAM, POR
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*/
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outb(0x9C, 0xF4000002);
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out_8(0x9C, 0xF4000002);
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/*
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* Enable UART0
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*/
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outb(0x20, 0xF4000003);
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out_8(0x20, 0xF4000003);
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/*
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* Cycle LEDs to show something is happening...
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*/
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outb(0x07, 0xF4000009);
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out_8(0x07, 0xF4000009);
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udelay(100000);
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outb(0x0B, 0xF4000009);
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out_8(0x0B, 0xF4000009);
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udelay(100000);
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outb(0x0D, 0xF4000009);
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out_8(0x0D, 0xF4000009);
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udelay(100000);
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outb(0x0E, 0xF4000009);
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out_8(0x0E, 0xF4000009);
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}
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@ -13,8 +13,7 @@ uses CONFIG_CHIP_CONFIGURE
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses CONFIG_USE_INIT
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uses CONFIG_CONSOLE_SERIAL8250
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uses TTYS0_BASE TTYS0_BAUD TTYS0_DIV
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uses UART0_IO_BASE
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uses TTYS0_BAUD TTYS0_DIV
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uses NO_POST
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uses CONFIG_IDE_STREAM
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uses CONFIG_SYS_CLK_FREQ
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@ -51,7 +50,6 @@ option NO_POST=1
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## Enable serial console
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option DEFAULT_CONSOLE_LOGLEVEL=8
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option CONFIG_CONSOLE_SERIAL8250=1
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option TTYS0_BASE={UART0_IO_BASE}
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# Divisor of 69 == 9600 baud due to weird clocking
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option TTYS0_DIV=69
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option TTYS0_BAUD=9600
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