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try to get memory mapped i/o to work 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson 2004-01-22 00:45:13 +00:00
parent 86da220788
commit c5acd90b53
3 changed files with 23 additions and 13 deletions
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20
src/mainboard/embeddedplanet/ep405pc/Config.lb
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@ -4,18 +4,30 @@
uses PCIC0_CFGADDR uses PCIC0_CFGADDR
uses PCIC0_CFGDATA uses PCIC0_CFGDATA
uses UART0_IO_BASE uses ISA_IO_BASE
uses ISA_MEM_BASE
uses TTYS0_BASE
uses _IO_BASE
## ##
## Set PCI registers ## Set PCI configuration register addresses
## ##
default PCIC0_CFGADDR=0xeec00000 default PCIC0_CFGADDR=0xeec00000
default PCIC0_CFGDATA=0xeec00004 default PCIC0_CFGDATA=0xeec00004
## ##
## Set UART base address ## Set PCI/ISA I/O and memory base address
## ##
default UART0_IO_BASE=0xef600300 default ISA_IO_BASE=0xe8000000
default ISA_MEM_BASE=0x80000000
default _IO_BASE=ISA_IO_BASE
##
## HACK ALERT: the UART0 registers are not in the PCI I/O address space
## but both IDE and UART use the same routines for I/O (inb/outb). To get
## around this we set TTYSO_BASE to the difference between the two.
##
default TTYS0_BASE=0xef600300-ISA_IO_BASE
## ##
## Early board initialization, called from ppc_main() ## Early board initialization, called from ppc_main()

12
src/mainboard/embeddedplanet/ep405pc/init.c
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@ -54,21 +54,21 @@ board_init(void)
/* /*
* Enable FLASH, NVRAM, POR * Enable FLASH, NVRAM, POR
*/ */
outb(0x9C, 0xF4000002); out_8(0x9C, 0xF4000002);
/* /*
* Enable UART0 * Enable UART0
*/ */
outb(0x20, 0xF4000003); out_8(0x20, 0xF4000003);
/* /*
* Cycle LEDs to show something is happening... * Cycle LEDs to show something is happening...
*/ */
outb(0x07, 0xF4000009); out_8(0x07, 0xF4000009);
udelay(100000); udelay(100000);
outb(0x0B, 0xF4000009); out_8(0x0B, 0xF4000009);
udelay(100000); udelay(100000);
outb(0x0D, 0xF4000009); out_8(0x0D, 0xF4000009);
udelay(100000); udelay(100000);
outb(0x0E, 0xF4000009); out_8(0x0E, 0xF4000009);
} }

4
targets/embeddedplanet/ep405pc/Config.lb
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@ -13,8 +13,7 @@ uses CONFIG_CHIP_CONFIGURE
uses DEFAULT_CONSOLE_LOGLEVEL uses DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_USE_INIT uses CONFIG_USE_INIT
uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BASE TTYS0_BAUD TTYS0_DIV uses TTYS0_BAUD TTYS0_DIV
uses UART0_IO_BASE
uses NO_POST uses NO_POST
uses CONFIG_IDE_STREAM uses CONFIG_IDE_STREAM
uses CONFIG_SYS_CLK_FREQ uses CONFIG_SYS_CLK_FREQ
@ -51,7 +50,6 @@ option NO_POST=1
## Enable serial console ## Enable serial console
option DEFAULT_CONSOLE_LOGLEVEL=8 option DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_CONSOLE_SERIAL8250=1 option CONFIG_CONSOLE_SERIAL8250=1
option TTYS0_BASE={UART0_IO_BASE}
# Divisor of 69 == 9600 baud due to weird clocking # Divisor of 69 == 9600 baud due to weird clocking
option TTYS0_DIV=69 option TTYS0_DIV=69
option TTYS0_BAUD=9600 option TTYS0_BAUD=9600