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amd/stoneyridge: Remove dead southbridge definitions 

The revision level is not checked.  This was probably left over from
trying to determine hudson variants.

Remove the unused SMI command port values.  This was missed in:
  e9b862e amd/stoneyridge: Use generic SMM command port values

Change-Id: I91d8051372f4e238d390dd445d0bf06d06683a66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Marshall Dawson 2017-11-09 17:21:05 -07:00 committed by Aaron Durbin
parent 870fe79e64
commit c5ada65620
1 changed files with 0 additions and 9 deletions
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9
src/soc/amd/stoneyridge/include/soc/southbridge.h
View File

@ -85,15 +85,6 @@
#define PM_LPC_A20_EN BIT(1) #define PM_LPC_A20_EN BIT(1)
#define PM_LPC_ENABLE BIT(0) #define PM_LPC_ENABLE BIT(0)
#define ACPI_SMI_CMD_CST_CONTROL 0xde
#define ACPI_SMI_CMD_PST_CONTROL 0xad
#define ACPI_SMI_CMD_DISABLE 0xbe
#define ACPI_SMI_CMD_ENABLE 0xef
#define ACPI_SMI_CMD_S4_REQ 0xc0
#define REV_STONEYRIDGE_A11 0x11
#define REV_STONEYRIDGE_A12 0x12
#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 #define SPIROM_BASE_ADDRESS_REGISTER 0xa0
#define ROUTE_TPM_2_SPI BIT(3) #define ROUTE_TPM_2_SPI BIT(3)
#define SPI_ABORT_ENABLE BIT(2) #define SPI_ABORT_ENABLE BIT(2)