nb/intel/snb: Abolish mainboard_should_reset_usb()

Of the 13 mainboards that implement mainboard_should_reset_usb() hook,
all but one do the same: Stop MRC from resetting USB when resuming
from S3 suspend.

This hook turns out is only here to facilitate a USB reset workaround
on samsung/stumpy for an old ChromeOS kernel which is no longer needed.

Drop the workaround, the hook, and headers no longer used.

roda/rv11/early_init.c is left with no useful code after this patch,
so drop it entirely from both bootblock and romstage.

Change-Id: Ib3a5a00c0a6b1528e39435784919223d16b3914e
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c

@@ -50,11 +50,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	read_spd(&spd[3], 0x53, id_only);
 }
 
-int mainboard_should_reset_usb(int s3resume)
-{
-	return !s3resume;
-}
-
 void mainboard_fill_pei_data(struct pei_data *pei)
 {
 	uint8_t spdaddr[] = {0xa0, 0xa2, 0xa4, 0xa6}; /* SMBus mul 2 */

src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c

@@ -56,11 +56,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	read_spd(&spd[3], 0x53, id_only);
 }
 
-int mainboard_should_reset_usb(int s3resume)
-{
-	return !s3resume;
-}
-
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
 	/*

src/mainboard/google/butterfly/early_init.c

@@ -116,8 +116,3 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 	};
 	*pei_data = pei_data_template;
 }
-
-int mainboard_should_reset_usb(int s3resume)
-{
-	return !s3resume;
-}

src/mainboard/google/link/early_init.c

@@ -166,8 +166,3 @@ void mainboard_early_init(int s3resume)
 		google_chromeec_kbbacklight(100);
 	}
 }
-
-int mainboard_should_reset_usb(int s3resume)
-{
-	return !s3resume;
-}

src/mainboard/google/parrot/early_init.c

@@ -118,8 +118,3 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	read_spd(&spd[0], 0x50, id_only);
 	read_spd(&spd[2], 0x52, id_only);
 }
-
-int mainboard_should_reset_usb(int s3resume)
-{
-	return !s3resume;
-}

src/mainboard/google/stout/early_init.c

@@ -144,11 +144,6 @@ void mainboard_early_init(int s3resume)
 	}
 }
 
-int mainboard_should_reset_usb(int s3resume)
-{
-	return !s3resume;
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	/* enabled   USB oc pin    length */
 	{1, 0, 0},  /* P0: USB 3.0 1  (OC0) */

src/mainboard/intel/dcp847ske/romstage.c

@@ -41,9 +41,4 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 	};
 	*pei_data = pei_data_template;
 }
-
-int mainboard_should_reset_usb(int s3resume)
-{
-	return !s3resume;
-}
 #endif

src/mainboard/intel/emeraldlake2/early_init.c

@@ -113,8 +113,3 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	read_spd(&spd[0], 0x50, id_only);
 	read_spd(&spd[2], 0x52, id_only);
 }
-
-int mainboard_should_reset_usb(int s3resume)
-{
-	return !s3resume;
-}

src/mainboard/kontron/ktqm77/early_init.c

@@ -136,8 +136,3 @@ void mainboard_early_init(int s3resume)
 			   pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) |
 			   DEVEN_PEG10);
 }
-
-int mainboard_should_reset_usb(int s3resume)
-{
-	return !s3resume;
-}

src/mainboard/lenovo/x220/early_init.c

@@ -2,7 +2,6 @@
 
 #include <arch/hpet.h>
 #include <stdint.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
@@ -56,8 +55,3 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	read_spd (&spd[0], 0x50, id_only);
 	read_spd (&spd[2], 0x51, id_only);
 }
-
-int mainboard_should_reset_usb(int s3resume)
-{
-	return !s3resume;
-}

src/mainboard/roda/rv11/Makefile.inc

@@ -8,5 +8,3 @@ romstage-y += variants/$(VARIANT_DIR)/early_init.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
-bootblock-y += early_init.c
-romstage-y += early_init.c

src/mainboard/roda/rv11/early_init.c

@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#include <southbridge/intel/bd82x6x/pch.h>
-
-int mainboard_should_reset_usb(int s3resume)
-{
-	return !s3resume;
-}

src/mainboard/samsung/lumpy/early_init.c

@@ -181,8 +181,3 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	/* read removable dimm spd */
 	read_spd(&spd[0], 0x50, id_only);
 }
-
-int mainboard_should_reset_usb(int s3resume)
-{
-	return !s3resume;
-}

src/mainboard/samsung/stumpy/cmos.layout

@@ -15,9 +15,6 @@ entries
 # coreboot config options: console
 395	4	e	6	debug_level
 
-# Stumpy USB reset workaround disable
-400	8	r	0	stumpy_usb_reset_disable
-
 # coreboot config options: southbridge
 408	1	e	1	nmi
 409	2	e	7	power_on_after_fail

src/mainboard/samsung/stumpy/early_init.c

@@ -15,15 +15,6 @@
 #include <southbridge/intel/common/gpio.h>
 #include <superio/smsc/lpc47n207/lpc47n207.h>
 
-/* Stumpy USB Reset Disable defined in cmos.layout */
-#if CONFIG(USE_OPTION_TABLE)
-#include "option_table.h"
-#define CMOS_USB_RESET_DISABLE  (CMOS_VSTART_stumpy_usb_reset_disable >> 3)
-#else
-#define CMOS_USB_RESET_DISABLE  (400 >> 3)
-#endif
-#define USB_RESET_DISABLE_MAGIC (0xdd) /* Disable if set to this */
-
 #define SUPERIO_DEV PNP_DEV(0x2e, 0)
 #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
@@ -164,31 +155,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 5 }, /* P13: Back port  (OC5) */
 };
 
-int mainboard_should_reset_usb(int s3resume)
-{
-	if (s3resume) {
-		/*
-		 * For Stumpy the back USB ports are reset on resume
-		 * so default to resetting the controller to make the
-		 * kernel happy.  There is a CMOS flag to disable the
-		 * controller reset in case the kernel can tolerate
-		 * the device power loss better in the future.
-		 */
-		u8 magic = cmos_read(CMOS_USB_RESET_DISABLE);
-		if (magic == USB_RESET_DISABLE_MAGIC) {
-			printk(BIOS_DEBUG, "USB Controller Reset Disabled\n");
-			return 0;
-		} else {
-			printk(BIOS_DEBUG, "USB Controller Reset Enabled\n");
-			return 1;
-		}
-	} else {
-		/* Ensure USB reset on resume is enabled at boot */
-		cmos_write(0, CMOS_USB_RESET_DISABLE);
-		return 1;
-	}
-}
-
 void bootblock_mainboard_early_init(void)
 {
 	if (CONFIG(DRIVERS_UART_8250IO))

src/northbridge/intel/sandybridge/raminit_mrc.c

@@ -328,7 +328,7 @@ void perform_raminit(int s3resume)
 	struct mrc_var_data *mrc_var;
 
 	/* Prepare USB controller early in S3 resume */
-	if (!mainboard_should_reset_usb(s3resume))
+	if (s3resume)
 		enable_usb_bar();
 
 	memset(&pei_data, 0, sizeof(pei_data));

src/northbridge/intel/sandybridge/sandybridge.h

@@ -65,7 +65,6 @@ void early_init_dmi(void);
 
 /* mainboard_early_init: Optional callback, run after console init but before raminit. */
 void mainboard_early_init(int s3resume);
-int mainboard_should_reset_usb(int s3resume);
 void perform_raminit(int s3resume);
 void report_memory_config(void);
 enum platform_type get_platform_type(void);