mb/google/octopus: Add device tree settings
Change-Id: Id45409a9561671237410dd2f8f0bbfe61ff33562 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/23846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Shamile Khan
Martin Roth
parent
bbb2a9551d
commit
c5f354b97b
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@ -2,4 +2,166 @@ chip soc/intel/apollolake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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# EMMC TX DATA Delay 1
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# Refer to EDS-Vol2-16.33.
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# [14:8] steps of delay for HS400, each 125ps.
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# [6:0] steps of delay for SDR104/HS200, each 125ps.
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register "emmc_tx_data_cntl1" = "0x0C3A"
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# EMMC TX DATA Delay 2
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# Refer to EDS-Vol2-16.34.
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# [30:24] steps of delay for SDR50, each 125ps.
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# [22:16] steps of delay for DDR50, each 125ps.
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# [14:8] steps of delay for SDR25/HS50, each 125ps.
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# [6:0] steps of delay for SDR12, each 125ps.
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register "emmc_tx_data_cntl2" = "0x28272929"
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# EMMC RX CMD/DATA Delay 1
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# Refer to EDS-Vol2-16.35.
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# [30:24] steps of delay for SDR50, each 125ps.
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# [22:16] steps of delay for DDR50, each 125ps.
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# [14:8] steps of delay for SDR25/HS50, each 125ps.
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# [6:0] steps of delay for SDR12, each 125ps.
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register "emmc_rx_cmd_data_cntl1" = "0x003B263B"
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# EMMC RX CMD/DATA Delay 2
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# Refer to EDS-Vol2-16.37.
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# [17:16] stands for Rx Clock before Output Buffer
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# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
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# [6:0] steps of delay for HS200, each 125ps.
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register "emmc_rx_cmd_data_cntl2" = "0x10008"
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# EMMC RX STROBE Delay
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# Refer to EDS-Vol2-16.36.
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# [16] Enable Auto Tuning for HS400 Strobe Path
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# [14:8] steps of delay for HS400 Mode 1, each 125ps.
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# [6:0] steps of delay for HS400 Mode 2, each 125ps.
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register "emmc_rx_strobe_cntl" = "0x0a0a"
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# EMMC TX COMMAND Delay
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# Refer to EDS-Vol2-16.32.
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# [14:8] steps of delay for DDR Mode, each 125ps.
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# [6:0] steps of delay for SDR Mode, each 125ps.
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register "emmc_tx_cmd_cntl" = "0x1305"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route, i.e., if this route changes then the affected GPE
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# offset bits also need to be changed. This sets the PMC register
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# GPE_CFG fields.
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register "gpe0_dw1" = "PMC_GPE_NW_63_32"
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register "gpe0_dw2" = "PMC_GPE_N_95_64"
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register "gpe0_dw3" = "PMC_GPE_NW_31_0"
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# Minimum SLP S3 assertion width 28ms.
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register "slp_s3_assertion_width_usecs" = "28000"
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# Enable lpss s0ix
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register "lpss_s0ix_enable" = "1"
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# digitizer at 400kHz
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register "i2c[0]" = "{
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 152,
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.fall_time_ns = 30,
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}"
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# trackpad at 400kHz
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register "i2c[6]" = "{
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 114,
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.fall_time_ns = 164,
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.data_hold_time_ns = 350,
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}"
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# touchscreen at 400kHz
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register "i2c[7]" = "{
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 76,
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.fall_time_ns = 164,
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}"
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device domain 0 on
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device pci 00.0 on end # - Host Bridge
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device pci 00.1 on end # - DPTF
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device pci 00.2 on end # - NPK
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device pci 02.0 on end # - Gen
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device pci 03.0 on end # - Iunit
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device pci 0c.0 on end # - CNVi
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device pci 0d.0 on end # - P2SB
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device pci 0d.1 on end # - PMC
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device pci 0d.2 on end # - Fast SPI
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device pci 0d.3 on end # - Shared SRAM
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device pci 0e.0 on end # - Audio
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device pci 0f.0 on end # - Heci1
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device pci 0f.1 on end # - Heci2
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device pci 0f.2 on end # - Heci3
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device pci 11.0 off end # - ISH
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device pci 12.0 off end # - SATA
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device pci 13.0 on end # - PCIe-A 0 Onboard M2 Slot(Wifi)
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device pci 13.1 off end # - PCIe-A 1
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device pci 13.2 off end # - PCIe-A 2
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device pci 13.3 off end # - PCIe-A 3
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device pci 14.0 off end # - PCIe-B 0
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device pci 14.1 off end # - PCIe-B 1
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device pci 15.0 on end # - XHCI
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device pci 15.1 off end # - XDCI
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device pci 16.0 on
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chip drivers/i2c/hid
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register "generic.hid" = ""WCOM50C1""
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register "generic.desc" = ""WCOM Digitizer""
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register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)"
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register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
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register "generic.has_power_resource" = "1"
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register "hid_desc_reg_offset" = "0x1"
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device i2c 0x9 on end
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end
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end # - I2C 0
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device pci 16.1 on end # - I2C 1
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device pci 16.2 on end # - I2C 2
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device pci 16.3 on end # - I2C 3
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device pci 17.0 off end # - I2C 4
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device pci 17.1 on end # - I2C 5
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device pci 17.2 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_135_IRQ)"
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register "wake" = "GPE0_DW2_02"
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register "probed" = "1"
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device i2c 15 on end
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end
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end # - I2C 6
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device pci 17.3 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0001""
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register "desc" = ""ELAN Touchscreen""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)"
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register "probed" = "1"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)"
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register "reset_delay_ms" = "20"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_213)"
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register "enable_delay_ms" = "1"
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register "has_power_resource" = "1"
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device i2c 10 on end
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end
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end # - I2C 7
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device pci 18.0 on end # - UART 0
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device pci 18.1 off end # - UART 1
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device pci 18.2 on end # - UART 2
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device pci 18.3 off end # - UART 3
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device pci 19.0 on end # - SPI 0
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device pci 19.1 off end # - SPI 1
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device pci 19.2 on end # - SPI 2
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device pci 1a.0 on end # - PWM
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device pci 1c.0 on end # - eMMC
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device pci 1e.0 off end # - SDIO
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device pci 1f.0 on
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end # - ESPI
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device pci 1f.1 on end # - SMBUS
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end
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end
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