mb/lenovo: Integrate W541 into haswell mainboard
Lots of code from lenovo/haswell can be reused for lenovo/w541. Thus, integrate it into lenovo/haswell and make it a variant. Change-Id: If99d842cff777fe27ff63baabc447e69b9d0333c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Felix Singer
parent
b5bdd70758
commit
c5f7055746
20 changed files with 14 additions and 321 deletions
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@ -24,6 +24,9 @@ config BOARD_LENOVO_THINKPAD_T440P
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select BOARD_LENOVO_HASWELL_COMMON
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select INTEL_INT15
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config BOARD_LENOVO_THINKPAD_W541
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select BOARD_LENOVO_HASWELL_COMMON
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if BOARD_LENOVO_HASWELL_COMMON
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config VBOOT
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@ -43,6 +46,7 @@ config VBOOT_VBNV_OFFSET
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config VARIANT_DIR
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default "t440p" if BOARD_LENOVO_THINKPAD_T440P
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default "w541" if BOARD_LENOVO_THINKPAD_W541
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config DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
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@ -55,10 +59,11 @@ config MAINBOARD_DIR
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config MAINBOARD_PART_NUMBER
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default "ThinkPad T440p" if BOARD_LENOVO_THINKPAD_T440P
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default "ThinkPad W541" if BOARD_LENOVO_THINKPAD_W541
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config VGA_BIOS_ID
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string
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default "8086,0416"
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default "8086,0416" if BOARD_LENOVO_THINKPAD_T440P
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config USBDEBUG_HCD_INDEX
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int
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@ -72,9 +77,13 @@ config PS2K_EISAID
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default "LEN0071"
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config PS2M_EISAID
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default "LEN0036"
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default "LEN0036" if BOARD_LENOVO_THINKPAD_T440P
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default "LEN004A" if BOARD_LENOVO_THINKPAD_W541
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config THINKPADEC_HKEY_EISAID
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default "LEN0068"
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config GFX_GMA_PANEL_1_PORT
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default "DP3" if BOARD_LENOVO_THINKPAD_W541
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endif
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@ -1,2 +1,5 @@
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config BOARD_LENOVO_THINKPAD_T440P
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bool "ThinkPad T440p"
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config BOARD_LENOVO_THINKPAD_W541
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bool "ThinkPad W541"
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@ -8,33 +8,6 @@
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#include <ec/lenovo/pmh7/pmh7.h>
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#include <device/pci_ops.h>
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void mainboard_config_rcba(void)
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{
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RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA);
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RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC);
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RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA);
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RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD);
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RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD);
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RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH);
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RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
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RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
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}
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void mb_late_romstage_setup(void)
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{
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u8 enable_peg = get_uint_option("enable_dual_graphics", 0);
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bool power_en = pmh7_dgpu_power_state();
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if (enable_peg != power_en)
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pmh7_dgpu_power_enable(!power_en);
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if (!enable_peg) {
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// Hide disabled dGPU device
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pci_and_config32(HOST_BRIDGE, DEVEN, ~DEVEN_D1F0EN);
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}
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}
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void mb_get_spd_map(struct spd_info *spdi)
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{
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spdi->addresses[0] = 0x50;
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@ -1,47 +0,0 @@
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if BOARD_LENOVO_THINKPAD_W541
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_12288
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select EC_LENOVO_H8
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select EC_LENOVO_PMH7
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select H8_HAS_BAT_THRESHOLDS_IMPL
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select H8_HAS_PRIMARY_FN_KEYS
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_CMOS_DEFAULT
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select HAVE_OPTION_TABLE
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select INTEL_GMA_HAVE_VBT
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select MAINBOARD_HAS_LIBGFXINIT
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select MAINBOARD_HAS_TPM1
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select MAINBOARD_USES_IFD_GBE_REGION
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select MEMORY_MAPPED_TPM
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select NORTHBRIDGE_INTEL_HASWELL
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select NO_UART_ON_SUPERIO
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select SERIRQ_CONTINUOUS_MODE
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select SOUTHBRIDGE_INTEL_LYNXPOINT
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select SYSTEM_TYPE_LAPTOP
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config GFX_GMA_PANEL_1_PORT
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default "DP3"
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config MAINBOARD_DIR
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default "lenovo/w541"
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config MAINBOARD_PART_NUMBER
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default "ThinkPad W541"
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config DRIVER_LENOVO_SERIALS
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bool
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default n
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config PS2K_EISAID
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default "LEN0071"
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config PS2M_EISAID
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default "LEN004A"
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config THINKPADEC_HKEY_EISAID
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default "LEN0068"
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endif
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@ -1,2 +0,0 @@
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config BOARD_LENOVO_THINKPAD_W541
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bool "ThinkPad W541"
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@ -1,2 +0,0 @@
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romstage-y += gpio.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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@ -1,4 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <ec/lenovo/h8/acpi/ec.asl>
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#include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl>
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@ -1,14 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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Method(_WAK,1)
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{
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/* ME may not be up yet. */
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\_TZ.MEB1 = 0
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\_TZ.MEB2 = 0
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Return(Package(){0,0})
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}
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Method(_PTS,1)
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{
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\_SB.PCI0.LPCB.EC.RADI(0)
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}
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@ -1,3 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <drivers/pc80/pc/ps2_controller.asl>
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@ -1,15 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi_gnvs.h>
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#include <soc/nvs.h>
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void mainboard_fill_gnvs(struct global_nvs *gnvs)
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{
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/* The lid is open by default. */
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gnvs->lids = 1;
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/* Temperature at which OS will shut down. */
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gnvs->tcrt = 100;
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/* Temperature at which OS will throttle CPU. */
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gnvs->tpsv = 90;
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}
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@ -1,13 +0,0 @@
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boot_option=Fallback
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debug_level=Debug
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power_on_after_fail=Disable
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nmi=Enable
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volume=0x3
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wlan=Enable
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fn_ctrl_swap=Disable
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f1_to_f12_as_primary=Enable
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sticky_fn=Disable
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trackpoint=Enable
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backlight=Keyboard
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enable_dual_graphics=Disable
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usb_always_on=Disable
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@ -1,76 +0,0 @@
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## SPDX-License-Identifier: GPL-2.0-only
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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# -----------------------------------------------------------------
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# coreboot config options: console
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395 4 e 6 debug_level
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#400 8 r 0 reserved for century byte
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 7 power_on_after_fail
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# coreboot config options: EC
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415 1 e 1 wlan
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416 1 e 1 trackpoint
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417 1 e 1 fn_ctrl_swap
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418 1 e 1 sticky_fn
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419 2 e 13 usb_always_on
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422 2 e 10 backlight
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424 1 e 1 f1_to_f12_as_primary
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# coreboot config options: northbridge
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435 1 e 1 enable_dual_graphics
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440 8 h 0 volume
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# VBOOT
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448 128 r 0 vbnv
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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4 0 Fallback
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4 1 Normal
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6 0 Emergency
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6 1 Alert
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6 2 Critical
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6 3 Error
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6 4 Warning
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6 5 Notice
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6 6 Info
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6 7 Debug
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6 8 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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# Haswell ThinkPads have no Thinklight
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#10 0 Both
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10 1 Keyboard
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#10 2 Thinklight only
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10 3 None
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13 0 Disable
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13 1 AC and battery
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13 2 AC only
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# -----------------------------------------------------------------
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checksums
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checksum 392 447 984
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@ -1,31 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
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#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
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#define EC_LENOVO_H8_ME_WORKAROUND 1
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#define THINKPAD_EC_GPE 17
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20141018 // OEM revision
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)
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{
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#include <acpi/dsdt_top.asl>
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#include "acpi/platform.asl"
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#include <cpu/intel/common/acpi/cpu.asl>
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#include <southbridge/intel/common/acpi/platform.asl>
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#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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Device (\_SB.PCI0)
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{
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#include <northbridge/intel/haswell/acpi/hostbridge.asl>
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#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
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#include <southbridge/intel/lynxpoint/acpi/pch.asl>
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}
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}
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@ -1,85 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <ec/acpi/ec.h>
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#include <ec/lenovo/h8/h8.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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#define GPE_EC_SCI 1
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#define GPE_EC_WAKE 13
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static void mainboard_smi_handle_ec_sci(void)
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{
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u8 status = inb(EC_SC);
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u8 event;
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if (!(status & EC_SCI_EVT))
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return;
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event = ec_query();
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printk(BIOS_DEBUG, "EC event %#02x\n", event);
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}
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void mainboard_smi_gpi(u32 gpi_sts)
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{
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if (gpi_sts & (1 << GPE_EC_SCI))
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mainboard_smi_handle_ec_sci();
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}
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/* lynxpoint doesn't have gpi_route_interrupt, so add it */
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#define GPI_DISABLE 0x00
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#define GPI_IS_SMI 0x01
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#define GPI_IS_SCI 0x02
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#define GPI_IS_NMI 0x03
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static void gpi_route_interrupt(u8 gpi, u8 mode)
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{
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u32 gpi_rout;
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gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
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gpi_rout &= ~(3 << (2 * gpi));
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gpi_rout |= ((mode & 3) << (2 * gpi));
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pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout);
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}
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int mainboard_smi_apmc(u8 data)
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{
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switch (data) {
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case APM_CNT_ACPI_ENABLE:
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/* use 0x1600/0x1604 to prevent races with userspace */
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ec_set_ports(0x1604, 0x1600);
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/* route EC_SCI to SCI */
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gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);
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/* discard all events, and enable attention */
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ec_write(0x80, 0x01);
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break;
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case APM_CNT_ACPI_DISABLE:
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/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
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provide a EC query function */
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ec_set_ports(0x66, 0x62);
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/* route EC_SCI to SMI */
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gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);
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/* discard all events, and enable attention */
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ec_write(0x80, 0x01);
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break;
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default:
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break;
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}
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return 0;
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}
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void mainboard_smi_sleep(u8 slp_typ)
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{
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if (slp_typ == 3) {
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u8 ec_wake = ec_read(0x32);
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/* If EC wake events are enabled,
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* enable wake on EC WAKE GPE. */
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if (ec_wake & 0x14) {
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/* Redirect EC WAKE GPE to SCI. */
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gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI);
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}
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}
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}
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